Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.

Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

Abstract: A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.

Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.

Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

Abstract: An integrated circuit includes a substrate, a well formed over a portion of the substrate, a stacked structure formed over a first portion of the well, a doped epi structure formed over a second portion of the well adjacent the stacked structure and below a plane defined by an upper surface of the first portion of the well, and a source/drain region formed over the doped epi structure.

Abstract: A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.

Abstract: A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.

Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

Abstract: A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.

Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.

Abstract: A differential filtering chromatic confocal microscopic system comprises a chromatic dispersion objective for receiving and axially dispersing a broadband light from a light source and projecting dispersed lights onto an object thereby forming an object light reflected therefrom; an optical modulation module for dividing the object light into a first and a second object lights; a pair of optical intensity sensing module, respectively having a spatial filter with a different pinhole diameter or a slit width from each other, for detecting the first and second object lights, thereby obtaining a plurality of first and second optical intensity signals; and a signal processor for respectively processing the plurality of first and second optical intensity signals thereby obtaining a plurality of differential rational values of optical intensity and determining a corresponding object depth associated with each differential rational value according to a relation between signal intensity ratio and object surface depth.

Abstract: The present invention provides measuring apparatus and method for three-dimensional profilometry of an object, wherein a random-speckle beam and a structured fringe beam are projected onto the object and reflected therefrom for forming deformed random-speckle beam and structured fringe beams that are separately acquired by an image acquiring device thereby obtaining a random-speckle image utilized to determine an absolute phase information of each position on the surface of the object, and a structured fringe image utilized to determine a relative phase information for each position of the surface of the object. Each absolute phase information and each relative phase information corresponding to each position are converted into an absolute depth and a relative depth, respectively. Finally, the depth information of each position on the surface of the object is calculated by combining the corresponding absolute depth and the relative depth whereby the surface profile of the object can be established.

Abstract: A chromatic confocal microscope system and signal process method is provided to utilize a first optical fiber module for modulating a light into a detecting light passing through a chromatic dispersion objective and thereby forming a plurality of chromatic dispersion lights to project onto an object. A second optical fiber module conjugated with the first optical fiber module receives a reflected object light for forming a filtered light, which is split into two filtered lights detected by two color sensing units for generating two sets of RGB intensity signals, wherein one set of RGB intensity signals is adjusted relative to the other set of RGB intensity signals. Then two sets of RGB intensity signals are calculated for obtaining a maximum ratio factor. Finally, according to the maximum ratio factor and a depth relation curve, the surface profile of the object can be reconstructed.

Abstract: The present invention provides measuring apparatus and method for three-dimensional profilometry of an object, wherein a random-speckle beam and a structured fringe beam are projected onto the object and reflected therefrom for forming deformed random-speckle beam and structured fringe beams that are separately acquired by an image acquiring device thereby obtaining a random-speckle image utilized to determine an absolute phase information of each position on the surface of the object, and a structured fringe image utilized to determine a relative phase information for each position of the surface of the object. Each absolute phase information and each relative phase information corresponding to each position are converted into an absolute depth and a relative depth, respectively. Finally, the depth information of each position on the surface of the object is calculated by combining the corresponding absolute depth and the relative depth whereby the surface profile of the object can be established.

Abstract: A differential filtering chromatic confocal microscopic system comprises a chromatic dispersion objective for receiving and axially dispersing a broadband light from a light source and projecting dispersed lights onto an object thereby forming an object light reflected therefrom; an optical modulation module for dividing the object light into a first and a second object lights; a pair of optical intensity sensing module, respectively having a spatial filter with a different pinhole diameter or a slit width from each other, for detecting the first and second object lights, thereby obtaining a plurality of first and second optical intensity signals; and a signal processor for respectively processing the plurality of first and second optical intensity signals thereby obtaining a plurality of differential rational values of optical intensity and determining a corresponding object depth associated with each differential rational value according to a relation between signal intensity ratio and object surface depth.