Patents by Inventor Liang-Chor Chung
Liang-Chor Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230363287Abstract: A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.Type: ApplicationFiled: July 17, 2023Publication date: November 9, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui TSOU, Zong-You LUO, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Publication number: 20230360686Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.Type: ApplicationFiled: July 14, 2023Publication date: November 9, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Zong-You LUO, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Patent number: 11778923Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.Type: GrantFiled: November 14, 2021Date of Patent: October 3, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui Tsou, Zong-You Luo, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
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Patent number: 11749328Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.Type: GrantFiled: July 25, 2022Date of Patent: September 5, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Zong-You Luo, Ya-Jui Tsou, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
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Publication number: 20220359372Abstract: The present disclosure describes an interconnect structure and a method forming the same. The interconnect structure can include a substrate, a layer of conductive material over the substrate, a metallic capping layer over the layer of conductive material, a layer of insulating material over top and side surfaces of the metallic capping layer, and a layer of trench conductor formed in the layer of insulating material and the metallic capping layer.Type: ApplicationFiled: July 22, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jason HUANG, Liang-Chor CHUNG, Cheng-Yuan LI
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Publication number: 20220358980Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Zong-You LUO, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Publication number: 20220352043Abstract: Test pad structures and methods of forming a test pad are described herein. A method for forming a test pad includes forming a device element over a substrate, depositing a dielectric layer over the device element and the substrate, and etching openings in the dielectric layer to a first depth. Once the openings have been formed, a conductive material is deposited in the openings and followed by a chemical mechanical planarization to form a first grid feature and a panel region of the test pad, the first grid feature extending lengthwise from the panel region to a perimeter of the test pad. Once formed, a probe may be used to contact the panel region of the test pad during a wafer acceptance test (WAT) and/or a process control monitoring (PCM) test of the device element.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Inventors: Yao-Te Huang, Liang-Chor Chung
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Patent number: 11476191Abstract: The present disclosure describes an interconnect structure and a method forming the same. The interconnect structure can include a substrate, a layer of conductive material over the substrate, a metallic capping layer over the layer of conductive material, a layer of insulating material over top and side surfaces of the metallic capping layer, and a layer of trench conductor formed in the layer of insulating material and the metallic capping layer.Type: GrantFiled: July 27, 2020Date of Patent: October 18, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jason Huang, Liang-Chor Chung, Cheng-Yuan Li
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Patent number: 11443991Abstract: Test pad structures and methods of forming a test pad are described herein. A method for forming a test pad includes forming a device element over a substrate, depositing a dielectric layer over the device element and the substrate, and etching openings in the dielectric layer to a first depth. Once the openings have been formed, a conductive material is deposited in the openings and followed by a chemical mechanical planarization to form a first grid feature and a panel region of the test pad, the first grid feature extending lengthwise from the panel region to a perimeter of the test pad. Once formed, a probe may be used to contact the panel region of the test pad during a wafer acceptance test (WAT) and/or a process control monitoring (PCM) test of the device element.Type: GrantFiled: May 29, 2020Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yao-Te Huang, Liang-Chor Chung
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Patent number: 11410714Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.Type: GrantFiled: September 16, 2019Date of Patent: August 9, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Zong-You Luo, Ya-Jui Tsou, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
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Publication number: 20220077384Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.Type: ApplicationFiled: November 14, 2021Publication date: March 10, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui TSOU, Zong-You LUO, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Publication number: 20210375703Abstract: Test pad structures and methods of forming a test pad are described herein. A method for forming a test pad includes forming a device element over a substrate, depositing a dielectric layer over the device element and the substrate, and etching openings in the dielectric layer to a first depth. Once the openings have been formed, a conductive material is deposited in the openings and followed by a chemical mechanical planarization to form a first grid feature and a panel region of the test pad, the first grid feature extending lengthwise from the panel region to a perimeter of the test pad. Once formed, a probe may be used to contact the panel region of the test pad during a wafer acceptance test (WAT) and/or a process control monitoring (PCM) test of the device element.Type: ApplicationFiled: May 29, 2020Publication date: December 2, 2021Inventors: Yao-Te Huang, Liang-Chor Chung
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Patent number: 11177430Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.Type: GrantFiled: June 17, 2019Date of Patent: November 16, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui Tsou, Zong-You Luo, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
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Publication number: 20210193565Abstract: The present disclosure describes an interconnect structure and a method forming the same. The interconnect structure can include a substrate, a layer of conductive material over the substrate, a metallic capping layer over the layer of conductive material, a layer of insulating material over top and side surfaces of the metallic capping layer, and a layer of trench conductor formed in the layer of insulating material and the metallic capping layer.Type: ApplicationFiled: July 27, 2020Publication date: June 24, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jason Huang, Liang-Chor Chung, Cheng-Yuan Li
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Publication number: 20210082482Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.Type: ApplicationFiled: September 16, 2019Publication date: March 18, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Zong-You LUO, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Publication number: 20200395530Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.Type: ApplicationFiled: June 17, 2019Publication date: December 17, 2020Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui TSOU, Zong-You LUO, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Patent number: 8529864Abstract: A process for hydrogen production at lower temperature by using Mn/ZnO, Cu/MnO, Cu/CeO2, CuCe/ZnO and/or CuMn/ZnO catalysts, wherein a partial oxidization of methanol (POM) process can be initiated at an ambient reactor temperature lower than 100° C. and then undertaken at a reaction temperature lower than 200° C., and wherein POM process not only generates hydrogen rich gas (HRG) containing 4% CO or less but also generates 1.8 moles hydrogen or more per 1 mole methanol consumed.Type: GrantFiled: August 26, 2011Date of Patent: September 10, 2013Assignee: National Tsing Hua UniversityInventors: Yuh-Jeen Huang, Chuin-Tih Yeh, Tsui-Wei Wang, Liang-Chor Chung
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Publication number: 20110311440Abstract: A process for hydrogen production at lower temperature by using Mn/ZnO, Cu/MnO, Cu/CeO2, CuCe/ZnO and/or CuMn/ZnO catalysts, wherein a partial oxidization of methanol (POM) process can be initiated at an ambient reactor temperature lower than 100° C. and then undertaken at a reaction temperature lower than 200° C., and wherein POM process not only generates hydrogen rich gas (HRG) containing 4% CO or less but also generates 1.8 moles hydrogen or more per 1 mole methanol consumed.Type: ApplicationFiled: August 26, 2011Publication date: December 22, 2011Inventors: Yuh-Jeen HUANG, Chuin-Tih YEH, Tsui-Wei WANG, Liang-Chor CHUNG
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Publication number: 20110212019Abstract: A self-started OSRM (oxidative steam reforming of methanol) process at evaporation temperature of aqueous methanol for hydrogen production is disclosed. In the process, an aqueous methanol steam and oxygen are pre-mixed. The mixture is then fed to a Cu/ZnO-based catalyst to initiate an OSRM process at evaporation temperature of aqueous methanol. The temperature of the catalyst bed, with suitable thermal isolation, may be raised automatically by the exothermic OSRM to enhance the conversion of methanol.Type: ApplicationFiled: May 13, 2011Publication date: September 1, 2011Inventors: Yuh-Jeen HUANG, Chuin-Tih Yeh, Chien-Te Ho, Liang-Chor Chung
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Publication number: 20100179056Abstract: A self-started OSRM (oxidative steam reforming of methanol) process at room temperature for hydrogen production. In the process, an aqueous methanol and oxygen are pre-mixed. The mixture is then fed to a Cu/ZnO-based catalyst to initiate an OSRM process at room temperature. The temperature of the catalyst bed, with suitable thermal isolation, may be raised automatically by the exothermic OSRM to enhance the conversion of methanol. A hydrogen yield of 2.4 moles per mole methanol from the process may be obtained.Type: ApplicationFiled: March 24, 2010Publication date: July 15, 2010Inventors: Yuh-Jeen HUANG, Chuin-Tih YEH, Chien-Te HO, Liang-Chor CHUNG