Abstract: The present invention provides a method for identifying radiation induced genes and long non-coding RNAs and its application thereof, the method comprises the steps of: (1). Provide expression values of genes and long non-coding RNAs; (2). Execute weighted gene correlation network analysis (WGCNA) by a computer system to calculate Pearson correlation coefficients of pairs of the genes and long non-coding RNAs based on the expression values of the genes and long non-coding RNAs; and (3). Perform a screening step by the computer system to identify radiation induced genes and long non-coding RNAs based on the Pearson correlation coefficients of the pairs of the genes and long non-coding RNAs with a value more than 0.75.

Abstract: A drug combination prediction method comprising: storing a plurality of original gene sets, at least one first gene impacted by a first drug and at least one second gene impacted by a second drug; determining the part of the at least one first gene and the part of the at least one second gene to be a first interaction gene set; calculating a gene amount of the first interaction gene set to obtain a first interaction gene amount, and calculating a first percentage generated by the first interaction gene amount in the first original gene set; calculating an interaction value of the combination of the first drug and the second drug according to the first percentage; and selecting at least one synergistic pharmaceutical composition according to the interaction value.

Abstract: The invention is directed to a method to predict prognostic results for diseases including acute myeloid leukemia (AML) by analyzing novel markers which comprises microRNA/mRNA (miRNA/mRNA) pairings. In particular, the miRNA/mRNA pairings are a kind of NPM1 mutation-modulated miRNA/mRNA regulation pairs.

Abstract: A system for analyzing sequencing data of bacterial strains and a method thereof are provided. The method for analyzing sequencing data of bacterial strains includes the following steps: searching a specific variable region of a first genetic sample sequence and searching another specific variable region of a second genetic sample sequence; determining whether both the specific variable region and the another specific variable region have an identical cross-sample subsequence; if both the specific variable region and the another specific variable region have the identical cross-sample subsequence, storing the cross-sample subsequence into a recording table; and if the identical cross-sample subsequence exists, comparing the cross-sample subsequence with a plurality of gene sequences of known strains stored in a database module to analyze a plurality of strains corresponding to the cross-sample subsequence in the first genetic sample sequence and the second genetic sample sequence.

Abstract: A method of manufacturing an isolation structure suitable for a non-volatile memory is provided. A substrate is provided. A dielectric layer, a conductive layer, and a hard mask layer are sequentially formed on the substrate. The hard mask layer and the conductive layer are patterned to form a first trench which exposes the dielectric layer. A first liner is formed on the substrate. The first liner and the dielectric layer that are exposed by the first trench are removed to expose the substrate. A spacer is formed on sidewalls of the conductive layer and the hard mask layer. The substrate is partly removed to form a second trench with use of the conductive layer and the hard mask layer with the spacer as a mask. An isolation layer is formed in the second trench. The distance between the conductive layers is greater than the width of the second trench.

Abstract: A method of manufacturing an isolation structure suitable for a non-volatile memory is provided. A substrate is provided. A dielectric layer, a conductive layer, and a hard mask layer are sequentially formed on the substrate. The hard mask layer and the conductive layer are patterned to form a first trench which exposes the dielectric layer. A first liner is formed on the substrate. The first liner and the dielectric layer that are exposed by the first trench are removed to expose the substrate. A spacer is formed on sidewalls of the conductive layer and the hard mask layer. The substrate is partly removed to form in a second trench with use of the conductive layer and the hard mask layer with the spacer as a mask. An isolation layer is formed in the second trench. The distance between the conductive layers is greater than the width of the second trench.

Abstract: The present invention relates to novel genetic markers associated with response of a patient with esophageal cancer (ECa) to chemoradiation therapy, and particularly to methods and kits for predicting an ECa patient's response to chemoradiation therapy by genotyping of the markers.

Abstract: The present invention relates to novel genetic markers associated with response of a patient with esophageal cancer (ECa) to chemoradiation therapy, and particularly to methods and kits for predicting an ECa patient's response to chemoradiation therapy by genotyping of the markers.

Abstract: The present invention relates to novel genetic markers associated with response of a patient with esophageal cancer (ECa) to chemoradiation therapy, and particularly to methods and kits for predicting an ECa patient's response to chemoradiation therapy by genotyping of the markers.

Abstract: A method for fabricating a memory is provided. A tunneling dielectric layer, a first conductive layer, and a mask layer are formed on a substrate. The mask layer, the first conductive layer, the tunneling dielectric layer, and the substrate are patterned to form trenches in the substrate. A passivation layer and isolation structures are formed in sequence to fill the trenches, and the etching rate of the isolation structures is greater than that of the passivation layer. After the mask layer is removed, a second conductive layer is formed on the first conductive layer. Portions of the isolation structures are removed to expose the sidewalls of the first and the second conductive layers. Further, a third conductive layer is formed on the exposed sidewalls of the first and the second conductive layers. An inter-gate dielectric layer and a control gate are formed on the substrate.

Abstract: A method of fabricating a non-volatile memory is provided. A substrate having a trench therein for forming a trench device is provided. Then, a doped metal silicide layer is formed on the substrate in the trench. A heating process is performed to form a source/drain area in the substrate under the doped metal silicide layer. Thereafter, a first conductive layer is formed on the doped metal silicide layer to fill up the trench.

Abstract: An anti-punch-through semiconductor device is provided. The anti-punch-through semiconductor device includes a substrate, at least an isolation region and a plurality of trench devices. The trench device is disposed in the substrate. The trench device includes a source/drain region. The source/drain region of the trench device is disposed at the bottom of the trench device. The isolation region is disposed in the substrate and between the source/drain regions of each trench device.

Abstract: A method of manufacturing self-aligned contact openings is provided. A substrate having a number of device structures is provided and the top of the device structures is higher than the surface of the substrate. A first dielectric layer and a conductive layer are sequentially formed on the surfaces of the substrate and the device structures. Next, a part of the conductive layers on the top and the sidewalls of the device structures is removed and a number of first spacers is formed on the exposed sidewalls of the device structures. The exposed conductive layer and the first dielectric layer are removed by using the first spacer as the mask to expose the substrate. Then, a number of conductive spacers is formed. A number of second spacers is formed on the sidewalls of the conductive spacers.

Abstract: An anti-punch-through semiconductor device is provided. The anti-punch-through semiconductor device includes a substrate, at least an isolation region and a plurality of trench devices. The trench device is disposed in the substrate. The trench device includes a source/drain region. The source/drain region of the trench device is disposed at the bottom of the trench device. The isolation region is disposed in the substrate and between the source/drain regions of each trench device.

Abstract: A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface of the floating gates is higher than that of the select gate forming a hollow structure on the select gate between the two floating gates. The control gate disposed on the substrate covers the select gate and the two floating gates and fills the hollow structure. The doped region is disposed in the substrate on one side of the two floating gates opposite to the select gate.

Abstract: A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface of the floating gates is higher than that of the select gate forming a hollow structure on the select gate between the two floating gates. The control gate disposed on the substrate covers the select gate and the two floating gates and fills the hollow structure. The doped region is disposed in the substrate on one side of the two floating gates opposite to the select gate.

Abstract: A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface of the floating gates is higher than that of the select gate forming a hollow structure on the select gate between the two floating gates. The control gate disposed on the substrate covers the select gate and the two floating gates and fills the hollow structure. The doped region is disposed in the substrate on one side of the two floating gates opposite to the select gate.

Abstract: A method for fabricating a wire with silicide is disclosed. First, a conductive layer is formed on a substrate. And, a hard mask layer is formed on the conductive layer. Then, the hard mask layer is used as a mask to remove a portion of the conductive layer. Afterwards, a spacer is formed on the sidewalls of the conductive layer and the hard mask layer. Afterwards, the hard mask layer is removed. Next, a silicide is formed on the conductive layer.

Abstract: A method of manufacturing self-aligned contact openings is provided. A substrate having a number of device structures is provided and the top of the device structures is higher than the surface of the substrate. A first dielectric layer and a conductive layer are sequentially formed on the surfaces of the substrate and the device structures. Next, a part of the conductive layers on the top and the sidewalls of the device structures is removed and a number of first spacers is formed on the exposed sidewalls of the device structures. The exposed conductive layer and the first dielectric layer are removed by using the first spacer as the mask to expose the substrate. Then, a number of conductive spacers is formed. A number of second spacers is formed on the sidewalls of the conductive spacers.

Abstract: A method of fabricating a semiconductor device is provided. Before covering the isolation structures with a conductive layer, a material layer is formed on the isolation structures. The fluid-like material layer allows the material layer formed between the isolation structures to be thicker than that formed on the top of the isolation structures. The isolation structures are then effectively etched back. The material layer at the top of the isolation structures is removed and a portion of isolation structures is also removed to lower the height of the isolation structures.