Abstract: Methods, systems, and devices for a light hibernation mode for memory are described. A memory system may include volatile memory and non-volatile memory and may be configured to operate according to a first mode of operation (e.g., associated with relatively high power consumption), a light hibernation mode (e.g., a second mode associated with decreased power consumption in comparison to the first mode), and a full hibernation mode (e.g., a third mode of operation associated with decreased power consumption in comparison to the light hibernation mode). While operating according to the light hibernation mode, the memory system may maintain a greater quantity of data in the volatile memory relative to the full hibernation mode, which may avoid at least some power consumption related to data transfers between the volatile memory and non-volatile memory that may occur in connection with entering and exiting the full hibernation mode.

Abstract: A method, computer system, and a computer program product are provided for backup and restoration of data. Data is obtained from a plurality of resources during a plurality of tasks. The resources are located in one or more computing networks. A plurality of parameters are extracted from obtained data. A table is generated and stored that includes the parameters extracted and an associated related task. A predict time is calculated based on the table for recovery of data when any of the resources become unavailable. A task priority is established based on calculated predict time and the table to optimize and improve the predict recovery time. A restoration model is generated based on updated restoration recommendation. The restoration model is to be used during resource unavailability or failure of one or more of the resources.

Abstract: Methods, systems, and devices for performance tuning for a memory device are described. In some examples, a memory system may receive a command (e.g., a read command or a write command) that includes an indicator. The indicator may instruct the memory system to suppress one or more portions of the command. For example, the command may be received by an interface of the memory system and the controller may instruct the memory system to suppress one or more operations performed by a processor of the memory system, a storage controller of the memory system, or both. Upon suppressing one or more operations associated with the command, the memory system may output a response to the test system, which may allow for the test system to tune one or more performance aspects of the memory system.

Abstract: Methods, systems, and devices for a light hibernation mode for memory are described. A memory system may include volatile memory and non-volatile memory and may be configured to operate according to a first mode of operation (e.g., associated with relatively high power consumption), a light hibernation mode (e.g., a second mode associated with decreased power consumption in comparison to the first mode), and a full hibernation mode (e.g., a third mode of operation associated with decreased power consumption in comparison to the light hibernation mode). While operating according to the light hibernation mode, the memory system may maintain a greater quantity of data in the volatile memory relative to the full hibernation mode, which may avoid at least some power consumption related to data transfers between the volatile memory and non-volatile memory that may occur in connection with entering and exiting the full hibernation mode.

Abstract: Methods, systems, and devices for performance tuning for a memory device are described. In some examples, a memory system may receive a command (e.g., a read command or a write command) that includes an indicator. The indicator may instruct the memory system to suppress one or more portions of the command. For example, the command may be received by an interface of the memory system and the controller may instruct the memory system to suppress one or more operations performed by a processor of the memory system, a storage controller of the memory system, or both. Upon suppressing one or more operations associated with the command, the memory system may output a response to the test system, which may allow for the test system to tune one or more performance aspects of the memory system.

Abstract: Devices, systems, and methods for removing or dividing valve leaflets, wherein the devices have an elongate shaft and a cutting tool disposed on or near a distal end of the shaft. Certain embodiments include a cutting tool comprising an expandable structure with a cutting element associated with the expandable structure. Other embodiments have a cutting tool that can extend out of an opening in the elongate shaft. Further implementations have a cutting tool that is a laser fiber, an ultrasound emitting tool, or a radiofrequency emitting tool. Some specific embodiments have a first expandable structure disposed at or near a distal end of the elongate shaft, and a second expandable structure disposed on the elongate shaft proximally of the first expandable structure, the second expandable structure comprising at least one distal projection, wherein the at least one distal projection comprises a cutting tool.

Abstract: Use of chaperones as autophagy receptors. The inventors identify a new function of the chaperones in aggrephagy. The chaperones are as a new type of autophagy receptor regulating the clearance of aggregation-prone proteins in cell and mouse brain.

Abstract: A positioner, a conveyor, a tunnel-type wire passing system and an operating method thereof. The positioner includes first and second locating rods, a guide wire and a drive unit. The first locating rod defines a first channel extending therethrough along its axial direction. The second locating rod is connected to the first locating rod. The second locating rod defines a second channel extending therethrough along its axial direction. A distal end of the second channel extending in a direction intersecting a direction in which a distal end of the first channel extends. The guide wire is movably inserted in the second channel along the axial direction of the second locating rod. The guide wire is provided at a distal end thereof with a connecting unit. The drive unit is connected to the guide wire and drives the guide wire to move in the axial direction of the second locating rod.

Abstract: Methods, systems, and devices for alignment of activation periods are described. Techniques for memory operations are described. A device may transition from a reduced-power state to a reception-ready state based on a timing parameter of the device that indicates a first duration for transitioning the device from the reduced-power state to the reception-ready state. After transitioning to the reception-ready state, a data transmission may be received beginning at a first time. A second time associated with an error in the data transmission may be determined. The timing parameter may be configured to indicate a second duration for transitioning the device to the reception-ready state based on a difference between the second time and the first time.

Abstract: An engagement and disengagement device used in a seat belt retractor including a first rotating member capable of being driven to rotate about a rotation axis thereof, a second rotating member provided coaxially with the first rotating member and connected to a reel of the seat belt retractor in an anti-torsion manner, and a transmission member provided between the first and second rotating member. The first rotating member is capable of transmitting torque to the second rotating member by means of the transmission member. The transmission member includes a holder and a transmission element in the holder. A first elastic component elastically holds the transmission element by radially exerting a force that enables the transmission element to be located away from the first or the second rotating member, and the first elastic component is integrated on the holder.

Abstract: Methods, systems, and devices for a light hibernation mode for memory are described. A memory system may include volatile memory and non-volatile memory and may be configured to operate according to a first mode of operation (e.g., associated with relatively high power consumption), a light hibernation mode (e.g., a second mode associated with decreased power consumption in comparison to the first mode), and a full hibernation mode (e.g., a third mode of operation associated with decreased power consumption in comparison to the light hibernation mode). While operating according to the light hibernation mode, the memory system may maintain a greater quantity of data in the volatile memory relative to the full hibernation mode, which may avoid at least some power consumption related to data transfers between the volatile memory and non-volatile memory that may occur in connection with entering and exiting the full hibernation mode.

Abstract: Methods, systems, and devices for cache allocation techniques are described. The memory system may receive a write command that includes a stream identification (ID) associated with performance constraints for data streams. The memory system may determine an application identification (ID) that indicates a type of data based on the stream ID of the write command. In some cases, the memory system may assign a level associated with the application ID that indicates an amount of data to be written for the write operation and allocate an amount of space available to be written for the write operation in a single-level cell cache based on the assigned level. The memory system may write the data to the single-level cell cache within the amount of space of the single-level cell cache.

Abstract: Methods, systems, and devices for alignment of activation periods are described. Techniques for memory operations are described. A device may transition from a reduced-power state to a reception-ready state based on a timing parameter of the device that indicates a first duration for transitioning the device from the reduced-power state to the reception-ready state. After transitioning to the reception-ready state, a data transmission may be received beginning at a first time. A second time associated with an error in the data transmission may be determined. The timing parameter may be configured to indicate a second duration for transitioning the device to the reception-ready state based on a difference between the second time and the first time.

Abstract: An engagement and disengagement device used in a seat belt retractor includes a first rotating member and a second rotating member configured to be coaxial, and a transmission member disposed between the first and second rotating members. The first rotating member defines an engagement portion on a radial inner surface thereof, and the distance from the engagement portion to an axis of rotation gradually increases in a first direction of rotation. The transmission member can rotate between an engagement position and a non-engagement position relative to the first rotating member.

Abstract: Methods, systems, and devices for performance tuning for a memory device are described. In some examples, a memory system may receive a command (e.g., a read command or a write command) that includes an indicator. The indicator may instruct the memory system to suppress one or more portions of the command. For example, the command may be received by an interface of the memory system and the controller may instruct the memory system to suppress one or more operations performed by a processor of the memory system, a storage controller of the memory system, or both. Upon suppressing one or more operations associated with the command, the memory system may output a response to the test system, which may allow for the test system to tune one or more performance aspects of the memory system.

Abstract: Methods, systems, and devices for cache allocation techniques are described. The memory system may receive a write command that includes a stream identification (ID) associated with performance constraints for data streams. The memory system may determine an application identification (ID) that indicates a type of data based on the stream ID of the write command. In some cases, the memory system may assign a level associated with the application ID that indicates an amount of data to be written for the write operation and allocate an amount of space available to be written for the write operation in a single-level cell cache based on the assigned level. The memory system may write the data to the single-level cell cache within the amount of space of the single-level cell cache.

Abstract: A downhole tool includes a receive antenna configured to receive a signal from a surrounding formation, and a receive amplifier proximate to and coupled to the receive antenna. The receive amplifier is configured to provide an amplified signal responsive to the signal received by the receive antenna. The downhole tool also includes an electronics carrier, including receive circuitry, coupled to the receive amplifier by a conductor. The electronics carrier is positioned axially away from the receive antenna and the receive amplifier, and the receive circuitry is configured to receive and process the amplified signal.

Abstract: A downhole tool includes a receive antenna configured to receive a signal from a surrounding formation, and a receive amplifier proximate to and coupled to the receive antenna. The receive amplifier is configured to provide an amplified signal responsive to the signal received by the receive antenna. The downhole tool also includes an electronics carrier, including receive circuitry, coupled to the receive amplifier by a conductor. The electronics carrier is positioned axially away from the receive antenna and the receive amplifier, and the receive circuitry is configured to receive and process the amplified signal.