Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract: A method of forming a semiconductor device using laser spike annealing is provided. The method includes providing a semiconductor substrate having a surface, forming a gate dielectric layer on the surface of the semiconductor substrate, laser spike annealing the gate dielectric layer, and patterning the gate dielectric layer and thus forming at least a gate dielectric. Source and drain regions are then formed to form a transistor. A capacitor is formed by connecting the source and drain regions.

Abstract: A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.

Abstract: A strained silicon layer fabrication employs a substrate having successively formed thereover: (1) a first silicon-germanium alloy material layer; (2) a first silicon layer; (3) a second silicon-germanium alloy material layer; and (4) a second silicon layer. Within the fabrication each of the first silicon-germanium alloy layer and the second silicon-germanium alloy layer is formed of a thickness less than a threshold thickness for dislocation defect formation, such as to provide attenuated dislocation defect formation within the strained silicon layer fabrication.

Abstract: A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.

Abstract: A semiconductor device and method for fabricating the same. The semiconductor device comprises a substrate with a gate stack thereon, wherein the gate stack comprises a high-k dielectric layer and a conductive layer sequentially overlying a portion of the substrate. An oxidation-proof layer overlies sidewalls of the gate stack. A pair of insulating spacers oppositely overlies sidewalls of the gate stack and the oxidation-proof layers thereon and a pair of source/drain regions is oppositely formed in the substrate adjacent to the gate stack, wherein the oxidation-proof layer suppresses oxidation encroachment between the gate stack and the substrate.

Abstract: A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.

Abstract: An alignment mark configuration, wherein the alignment mark is protected from being damaged from the subsequent planarization process, is described. The alignment mark configuration comprises a plurality of recesses and a flat spacing between the recesses on the substrate. If the substrate further comprises a trench structure, the spacing between the trench structure and the alignment mark is at least 5 times the flat spacing between the neighboring recesses of the alignment mark.

Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Abstract: A method of making a semiconductor device having a silicon dioxide based gate with improved dielectric properties including providing a silicon based substrate having active areas defined therein. Thermally growing a silicon dioxide based gate from the silicon based substrate. Nitriding the silicon dioxide based gate to provide a nitrided silicon dioxide based gate and to increase the dielectric constant of the silicon dioxide based gate without substantially increasing thickness of the silicon dioxide based gate.

Abstract: A method for making an improved silicon-germanium layer on a substrate for the base of a heterojunction bipolar transistor is achieved using a two-temperature process. The method involves growing a seed layer at a higher temperature to reduce the grain size with shorter reaction times, and then growing an epitaxial Si—Ge layer with a Si cap layer at a lower temperature to form the intrinsic base with low boron out-diffusion. This results in an HBT having the desired narrow base profile while minimizing the discontinuities (voids) in the Si—Ge layer over the insulator to provide good electrical contacts and uniformity to the intrinsic base.

Abstract: A method for forming a strained silicon layer device with improved wafer throughput and low defect density including providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane and silane.

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract: A method for forming a strained silicon layer device with improved wafer throughput and low defect density including providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane and silane.

Abstract: A silicon strained channel MOSFET device and method for forming the same the method providing improved wafer throughput and low defect density including the steps of providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane.

Abstract: A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

Abstract: A method of forming an Si—Ge epitaxial layer comprising the following steps. A structure is provided and a doped Si—Ge seed layer is formed thereover. The doped Si—Ge seed layer having increased nucleation sites. A Si—Ge epitaxial layer upon the doped Si—Ge seed layer whereby the Si—Ge epitaxial layer lacks discontinuity.

Abstract: A method for making an improved silicon-germanium layer on a substrate for the base of a heterojunction bipolar transistor is achieved using a two-temperature process. The method involves growing a seed layer at a higher temperature to reduce the grain size with shorter reaction times, and then growing an epitaxial Si—Ge layer with a Si pap layer at a lower temperature to form the intrinsic base with low boron out-diffusion. This results in an HBT having the desired narrow base profile while minimizing the discontinuities (voids) in the Si—Ge layer over the insulator to provide good electrical contacts and uniformity to the intrinsic base.

Abstract: A method of forming an Si—Ge epitaxial layer comprising the following steps. A structure is provided and a doped Si—Ge seed layer is formed thereover. The doped Si—Ge seed layer having increased nucleation sites. A Si—Ge epitaxial layer upon the doped Si—Ge seed layer whereby the Si—Ge epitaxial layer lacks discontinuity.