Abstract: A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (STV) signal and a base STV signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time. A compare unit determines whether frequencies of the two state signals are same, so that the select unit determines to forward the base trigger signal or the switch trigger signal to a level shift circuit. Finally, a signal-time control unit controls an output time of the base trigger signal, and controls an output time of the switch trigger signal, so that a liquid crystal unit connected to each gate line has an equal charge time.

Abstract: A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (STV) signal and a base STV signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time. A compare unit determines whether frequencies of the two state signals are same, so that the select unit determines to forward the base trigger signal or the switch trigger signal to a level shift circuit. Finally, a signal-time control unit controls an output time of the base trigger signal, and controls an output time of the switch trigger signal, so that a liquid crystal unit connected to each gate line has an equal charge time.

Abstract: A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (STV) signal and a base STV signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time. A compare unit determines whether frequencies of the two state signals are same, so that the select unit determines to forward the base trigger signal or the switch trigger signal to a level shift circuit. Finally, a signal-time control unit controls an output time of the base trigger signal, and controls an output time of the switch trigger signal, so that a liquid crystal unit connected to each gate line has an equal charge time.

Abstract: A noise cancellation circuit includes at least one antenna, a multiplexer, and a readout circuit. The at least one antenna is used for coupling noise of a touch panel and noise of a liquid crystal panel coupled to the touch panel. The multiplexer is used for receiving first X axis sensing signals and first Y axis sensing signals of the touch panel. The readout circuit is used for utilizing the noise of the touch panel and the noise of the liquid crystal panel to cancel noise of the touch panel and noise of the liquid crystal panel in the first X axis sensing signals and the first Y axis sensing signals, and to generate and output second X axis sensing signals and second Y axis sensing signals not including the noise of the touch panel and the noise of the liquid crystal panel.

Abstract: A shading signal generating circuit includes an output port, a first switch, a second switch, a third switch, a first control unit, a second control unit, and a resistor. The output port is electrically connected to the first switch, the second switch, and the third switch. The first switch is electrically connected to a first voltage source and switched on according to a clock signal. The second switch is electrically connected to a second voltage source. The first control unit converts the clock signal to an inverse clock signal, thereby outputting a switch signal for switching on the second switch. The resistor is connected between a third voltage source and the third switch in series. The third switch controls the electric connection between the output port and the third voltage source. The second control unit switches on the third switch according to the inverse clock signal and the switch signal.

Abstract: A noise cancellation circuit includes at least one antenna, a multiplexer, and a readout circuit. The at least one antenna is used for coupling noise of a touch panel and noise of a liquid crystal panel coupled to the touch panel. The multiplexer is used for receiving first X axis sensing signals and first Y axis sensing signals of the touch panel. The readout circuit is used for utilizing the noise of the touch panel and the noise of the liquid crystal panel to cancel noise of the touch panel and noise of the liquid crystal panel in the first X axis sensing signals and the first Y axis sensing signals, and to generate and output second X axis sensing signals and second Y axis sensing signals not including the noise of the touch panel and the noise of the liquid crystal panel.

Abstract: A gate driving circuit of a display panel including a plurality of shift register sets coupled in series is provided. Every shift register set includes a shift register unit and a transistor coupled therewith. The shift register units receive a gate timing signal and an inverted gate timing signal, and one of a first level shift register unit and a last level shift register unit further receives a threshold driving signal. The shift register units respectively output a plurality of gate driving signals sequentially according to the threshold driving signal, the gate timing signal and the inverted gate timing signal. A gate and a first source/drain of each transistor are coupled to receive a gate controlling signal, and a second source/drain of each transistor is coupled to the corresponding shift register unit to output one of the gate driving signals.

Abstract: A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (STV) signal and a base STV signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time. A compare unit determines whether frequencies of the two state signals are same, so that the select unit determines to forward the base trigger signal or the switch trigger signal to a level shift circuit. Finally, a signal-time control unit controls an output time of the base trigger signal, and controls an output time of the switch trigger signal, so that a liquid crystal unit connected to each gate line has an equal charge time.

Abstract: A shading signal generating circuit includes an output port, a first switch, a second switch, a third switch, a first control unit, a second control unit, and a resistor. The output port is electrically connected to the first switch, the second switch, and the third switch. The first switch is electrically connected to a first voltage source and switched on according to a clock signal. The second switch is electrically connected to a second voltage source. The first control unit converts the clock signal to an inverse clock signal, thereby outputting a switch signal for switching on the second switch. The resistor is connected between a third voltage source and the third switch in series. The third switch controls the electric connection between the output port and the third voltage source. The second control unit switches on the third switch according to the inverse clock signal and the switch signal.

Abstract: An LCD includes a PWB, a FPC, and a display panel. The PWB includes a level shift circuit and a power-off discharge circuit. The display panel includes a gate driving circuit and a TFT array. The power-off discharge circuit can electrically connects a gate high voltage end to a gate low voltage end so as to drive the gate driving circuit to turn on all TFTs of the TFT array.

Abstract: A display including a control circuit, a first gate driver, a second gate driver, and pixel unit groups is provided. Each pixel unit group includes a first pixel unit, a second pixel unit, a third pixel unit and a fourth pixel unit. The control circuit provides a first start signal and a second start signal to the first gate driver and the second gate driver respectively. In a first frame period, the first start signal is provided, and then after a period, the second start signal is provided to drive the first pixel unit, the second pixel unit, the third pixel unit and the fourth pixel unit sequentially. In a second frame period, the second start signal is provided, and then after a period, the first start signal is provided to drive the second pixel unit, the first pixel unit, the fourth pixel unit and the third pixel unit sequentially.

Abstract: A gate driving circuit of a display panel including a plurality of shift register sets coupled in series is provided. Every shift register set includes a shift register unit and a transistor coupled therewith. The shift register units receive a gate timing signal and an inverted gate timing signal, and one of a first level shift register unit and a last level shift register unit further receives a threshold driving signal. The shift register units respectively output a plurality of gate driving signals sequentially according to the threshold driving signal, the gate timing signal and the inverted gate timing signal. A gate and a first source/drain of each transistor are coupled to receive a gate controlling signal, and a second source/drain of each transistor is coupled to the corresponding shift register unit to output one of the gate driving signals.

Abstract: An LCD includes a PWB, a FPC, and a display panel. The PWB includes a level shift circuit and a power-off discharge circuit. The display panel includes a gate driving circuit and a TFT array. The power-off discharge circuit can electrically connects a gate high voltage end to a gate low voltage end so as to drive the gate driving circuit to turn on all TFTs of the TFT array.

Abstract: The present invention provides a voltage divider circuit capable of reducing a number of external devices and lowering the cost and power consumption. The present invention includes a plurality of resistors connected in series, a plurality of buffers and at least one source driver IC. In addition, a first terminal of the first resistor is electrically connected to a DC voltage and the first terminal of each of the remaining resistors is electrically connected to the second terminal of the previous resistor. The second terminal of the last resistor is grounded. The buffers and the resistors are correspondingly electrically connected, wherein the first terminals of the resistors are electrically connected to their corresponding input terminals of buffers. Moreover, the output terminals of the buffers are electrically connected to source driver ICs, wherein the buffers are one of the built-in buffers in each source driver IC.

Abstract: The invention is directed to a driving method for an LCD device, including conducting two of the gate driving lines respectively controlled by different gate integrated circuits. Then, it is determined that one of the two conducted gate driving lines is applied with the scan signal, according to a first output enabling signal and a second output enabling signal being received. A latch signal is received, wherein during a period at a high logic level of the latch signal, the adjacent source driving lines are shorted.

Abstract: A system for reducing the residual image effect of a liquid crystal display after turned off is described, which includes a timing controller, a source driver, a gate driver, and a plurality of thin film transistors on the panel of the liquid crystal display. The system first transmits an image signal to the panel of the liquid crystal display by means of the timing controller in a period of time from when a backlight of the liquid crystal display is turned off to when an image data transmission is turned off. The system then transmits a control signal to the gate driver through the timing controller to turn on all the thin film transistors during a period of time from when the image data transmission is turned off to when the power to the liquid crystal display is turned off. Therefore, residual electric charges in the thin film transistors are discharged rapidly via a plurality of source lines of the source driver, and the residual image effect is consequently diminished.

Abstract: A DAC and a source driver using the same, and a driving method for a display device are provided. The DAC comprises a positive polarity resistor string and a negative polarity resistor string. The resistance of each resistor of the positive polarity resistor string is determined based on positive polarity driving voltages. The resistance of each resistor of the negative polarity resistor string is determined based on negative polarity driving voltages. So, the positive and negative polarity driving voltages, which are used for driving the display device, are in symmetric.

Abstract: The present invention provides a voltage divider circuit capable of reducing a number of external devices and lowering the cost and power consumption. The present invention includes a plurality of resistors connected in series, a plurality of buffers and at least one source driver IC. In addition, a first terminal of the first resistor is electrically connected to a DC voltage and the first terminal of each of the remaining resistors is electrically connected to the second terminal of the previous resistor. The second terminal of the last resistor is grounded. The buffers and the resistors are correspondingly electrically connected, wherein the first terminals of the resistors are electrically connected to their corresponding input terminals of buffers. Moreover, the output terminals of the buffers are electrically connected to source driver ICs, wherein the buffers are one of the built-in buffers in each source driver IC.

Abstract: The present invention provides a voltage divider circuit capable of reducing a number of external devices and lowering the cost and power consumption. The present invention includes a plurality of resistors connected in series, a plurality of buffers and at least one source driver IC. In addition, a first terminal of the first resistor is electrically connected to a DC voltage and the first terminal of each of the remaining resistors is electrically connected to the second terminal of the previous resistor. The second terminal of the last resistor is grounded. The buffers and the resistors are correspondingly electrically connected, wherein the first terminals of the resistors are electrically connected to their corresponding input terminals of buffers. Moreover, the output terminals of the buffers are electrically connected to source driver ICs, wherein the buffers are one of the built-in buffers in each source driver IC.

Abstract: A charge-sharing method and apparatus for display panel including at least two data channels are provided. The charge-sharing method includes the following steps. First, one data channel is connected with another data channel at a first time-point of a period during which the pixels are turned on. The connections among the data channels are turned off at a second time-point of the period during which the pixels are turned on. Thereby, the display signal can be transmitted to the data channel in the display panel.