Abstract: In accordance with one aspect of the present description, an indication that a communication failure reported in a predetermined time interval is more likely the result of a software failure than a hardware failure may be made if the number of communication links reporting a communication failure in the predetermined time interval exceeds a communication link failure threshold, and the number of communication link devices such as nodes or communication paths which have been implicated as causing a communication failure, exceeds an implicated device threshold. Other features and aspects may be realized, depending upon the particular application.

Abstract: A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (STV) signal and a base STV signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time. A compare unit determines whether frequencies of the two state signals are same, so that the select unit determines to forward the base trigger signal or the switch trigger signal to a level shift circuit. Finally, a signal-time control unit controls an output time of the base trigger signal, and controls an output time of the switch trigger signal, so that a liquid crystal unit connected to each gate line has an equal charge time.

Abstract: In accordance with one aspect of the present description, an indication that a communication failure reported in a predetermined time interval is more likely the result of a software failure than a hardware failure may be made if the number of communication links reporting a communication failure in the predetermined time interval exceeds a communication link failure threshold, and the number of communication link devices such as nodes or communication paths which have been implicated as causing a communication failure, exceeds an implicated device threshold. Other features and aspects may be realized, depending upon the particular application.

Abstract: Disclosed herein is a radio frequency shield device that includes, an outer cover having one or more displacement protrusions extending from an outer cover bottom surface and one or more cover fasteners, an inner cover positioned inside the outer cover, wherein at least a portion of the inner cover is deflected downward by the displacement protrusions, and a plurality of fence walls having one or more fence fasteners for interlocking with the cover fasteners, wherein the inner cover is positioned at least partially over the fence walls to form at least one of a primary seal and secondary seal.

Abstract: A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (STV) signal and a base STV signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time. A compare unit determines whether frequencies of the two state signals are same, so that the select unit determines to forward the base trigger signal or the switch trigger signal to a level shift circuit. Finally, a signal-time control unit controls an output time of the base trigger signal, and controls an output time of the switch trigger signal, so that a liquid crystal unit connected to each gate line has an equal charge time.

Abstract: A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (STV) signal and a base STV signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time. A compare unit determines whether frequencies of the two state signals are same, so that the select unit determines to forward the base trigger signal or the switch trigger signal to a level shift circuit. Finally, a signal-time control unit controls an output time of the base trigger signal, and controls an output time of the switch trigger signal, so that a liquid crystal unit connected to each gate line has an equal charge time.

Abstract: In accordance with one aspect of the present description, an indication that a communication failure reported in a predetermined time interval is more likely the result of a software failure than a hardware failure may be made if the number of communication links reporting a communication failure in the predetermined time interval exceeds a communication link failure threshold, and the number of communication link devices such as nodes or communication paths which have been implicated as causing a communication failure, exceeds an implicated device threshold. Other features and aspects may be realized, depending upon the particular application.

Abstract: A noise cancellation circuit includes at least one antenna, a multiplexer, and a readout circuit. The at least one antenna is used for coupling noise of a touch panel and noise of a liquid crystal panel coupled to the touch panel. The multiplexer is used for receiving first X axis sensing signals and first Y axis sensing signals of the touch panel. The readout circuit is used for utilizing the noise of the touch panel and the noise of the liquid crystal panel to cancel noise of the touch panel and noise of the liquid crystal panel in the first X axis sensing signals and the first Y axis sensing signals, and to generate and output second X axis sensing signals and second Y axis sensing signals not including the noise of the touch panel and the noise of the liquid crystal panel.

Abstract: A shading signal generating circuit includes an output port, a first switch, a second switch, a third switch, a first control unit, a second control unit, and a resistor. The output port is electrically connected to the first switch, the second switch, and the third switch. The first switch is electrically connected to a first voltage source and switched on according to a clock signal. The second switch is electrically connected to a second voltage source. The first control unit converts the clock signal to an inverse clock signal, thereby outputting a switch signal for switching on the second switch. The resistor is connected between a third voltage source and the third switch in series. The third switch controls the electric connection between the output port and the third voltage source. The second control unit switches on the third switch according to the inverse clock signal and the switch signal.

Abstract: A noise cancellation circuit includes at least one antenna, a multiplexer, and a readout circuit. The at least one antenna is used for coupling noise of a touch panel and noise of a liquid crystal panel coupled to the touch panel. The multiplexer is used for receiving first X axis sensing signals and first Y axis sensing signals of the touch panel. The readout circuit is used for utilizing the noise of the touch panel and the noise of the liquid crystal panel to cancel noise of the touch panel and noise of the liquid crystal panel in the first X axis sensing signals and the first Y axis sensing signals, and to generate and output second X axis sensing signals and second Y axis sensing signals not including the noise of the touch panel and the noise of the liquid crystal panel.

Abstract: Disclosed herein is a radio frequency shield device that includes, an outer cover having one or more displacement protrusions extending from an outer cover bottom surface and one or more cover fasteners, an inner cover positioned inside the outer cover, wherein at least a portion of the inner cover is deflected downward by the displacement protrusions, and a plurality of fence walls having one or more fence fasteners for interlocking with the cover fasteners, wherein the inner cover is positioned at least partially over the fence walls to form at least one of a primary seal and secondary seal.

Abstract: A gate driving circuit of a display panel including a plurality of shift register sets coupled in series is provided. Every shift register set includes a shift register unit and a transistor coupled therewith. The shift register units receive a gate timing signal and an inverted gate timing signal, and one of a first level shift register unit and a last level shift register unit further receives a threshold driving signal. The shift register units respectively output a plurality of gate driving signals sequentially according to the threshold driving signal, the gate timing signal and the inverted gate timing signal. A gate and a first source/drain of each transistor are coupled to receive a gate controlling signal, and a second source/drain of each transistor is coupled to the corresponding shift register unit to output one of the gate driving signals.

Abstract: A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (STV) signal and a base STV signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time. A compare unit determines whether frequencies of the two state signals are same, so that the select unit determines to forward the base trigger signal or the switch trigger signal to a level shift circuit. Finally, a signal-time control unit controls an output time of the base trigger signal, and controls an output time of the switch trigger signal, so that a liquid crystal unit connected to each gate line has an equal charge time.

Abstract: A shading signal generating circuit includes an output port, a first switch, a second switch, a third switch, a first control unit, a second control unit, and a resistor. The output port is electrically connected to the first switch, the second switch, and the third switch. The first switch is electrically connected to a first voltage source and switched on according to a clock signal. The second switch is electrically connected to a second voltage source. The first control unit converts the clock signal to an inverse clock signal, thereby outputting a switch signal for switching on the second switch. The resistor is connected between a third voltage source and the third switch in series. The third switch controls the electric connection between the output port and the third voltage source. The second control unit switches on the third switch according to the inverse clock signal and the switch signal.

Abstract: An LCD includes a PWB, a FPC, and a display panel. The PWB includes a level shift circuit and a power-off discharge circuit. The display panel includes a gate driving circuit and a TFT array. The power-off discharge circuit can electrically connects a gate high voltage end to a gate low voltage end so as to drive the gate driving circuit to turn on all TFTs of the TFT array.

Abstract: An extract prepared from the root barks of Morus australis Poir.

Abstract: A display including a control circuit, a first gate driver, a second gate driver, and pixel unit groups is provided. Each pixel unit group includes a first pixel unit, a second pixel unit, a third pixel unit and a fourth pixel unit. The control circuit provides a first start signal and a second start signal to the first gate driver and the second gate driver respectively. In a first frame period, the first start signal is provided, and then after a period, the second start signal is provided to drive the first pixel unit, the second pixel unit, the third pixel unit and the fourth pixel unit sequentially. In a second frame period, the second start signal is provided, and then after a period, the first start signal is provided to drive the second pixel unit, the first pixel unit, the fourth pixel unit and the third pixel unit sequentially.

Abstract: A gate driving circuit of a display panel including a plurality of shift register sets coupled in series is provided. Every shift register set includes a shift register unit and a transistor coupled therewith. The shift register units receive a gate timing signal and an inverted gate timing signal, and one of a first level shift register unit and a last level shift register unit further receives a threshold driving signal. The shift register units respectively output a plurality of gate driving signals sequentially according to the threshold driving signal, the gate timing signal and the inverted gate timing signal. A gate and a first source/drain of each transistor are coupled to receive a gate controlling signal, and a second source/drain of each transistor is coupled to the corresponding shift register unit to output one of the gate driving signals.