Abstract: A multi-input power system receives at least two input power sources, and includes at least two filter and rectification circuits, at least two boost PFC circuits, a DC-to-DC conversion circuit, and a control circuit. The filter and rectification circuits correspondingly receive the input power sources, and convert the input power sources into rectified voltages. The boost PFC circuits correspondingly receive the rectified voltages and perform a power factor correction on the rectified voltages to provide a conversion voltage. The DC-to-DC conversion circuit converts the conversion voltage into an output voltage. The control circuit receives power information corresponding to the input power sources and determines power supply status of the input power sources according to the power information to generate control signals. The control signals are provided to correspondingly control the boost PFC circuits to control the magnitude of the conversion voltage.

Abstract: A power converter receives an input voltage. The power converter includes a boost power factor correction (PFC) circuit, a DC-to-DC conversion circuit, a bypass switch, and a comparison circuit. The comparison circuit receives the input voltage and a voltage threshold, and compares the input voltage with the voltage threshold to generate a first control signal and a second control signal. When the input voltage is greater than or equal to the voltage threshold, the first control signal turns on the bypass switch and the second control signal disables the boost PFC circuit so that the input voltage is provided to the DC-to-DC conversion circuit and is converted into an output voltage by the DC-to-DC conversion circuit.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A glue spreader is disclosed. It is a tubular structure with a body. The body tapers from a first open end to a second open end. A cross-sectional shape of the body gradually changes from a perfect circle at the first open end to an oblate circle at the second open end. The second open end forms a flow guiding curved plate outwards, the flow guiding curved plate extends in a direction vertical to an extending direction of the body and forms two symmetrical curved surfaces, and a straight-line section is formed at the end of each curved surface. The first open end is used to connect to a bottle mouth of a glue bottle of an adhesive glue.

Abstract: A common-mode noise cancellation circuit includes a capacitor and an inductor. The inductor has a three coupled winding, including a first coupled winding, a second coupled winding, and a third coupled winding. An input end of the first coupled winding and an input end of the second coupled winding are respectively coupled to two ends of an input power source. An input end of the third coupled winding is coupled to the output end of the second coupled winding, and an output end of the third coupled winding is coupled to the capacitor. An output end of the first coupled winding and an output end of the second coupled winding are respectively coupled to two input ends of a power conversion stage.

Abstract: A multi-input power system with an inrush current suppression function receives at least two input power sources, and includes at least two filter-rectification circuits, at least two boost PFC circuits, a current suppression circuit, and a DC-to-DC conversion circuit. Each filter-rectification circuit correspondingly receives the input power source, and converts the at least two input power sources into at least two rectified voltages. Each boost PFC circuit is correspondingly connected to the filter-rectification circuit, receives the rectified voltage, and performs a power factor correction to the rectified voltage to provide a conversion voltage. The current suppression circuit is connected to the at least two filter-rectification circuits and the at least two boost PFC circuits. The DC-to-DC is connected to the at least two boost PFC circuits and the current suppression circuit, receives the conversion voltage and converts the conversion voltage into an output voltage.

Abstract: A multi-input power system receives at least two input power sources, and includes at least two filter-rectification circuits, a switching switch, a boost power factor correction circuit, a DC-to-DC conversion circuit, a determination circuit, and a switch control circuit. The at least two filter-rectification circuits correspondingly convert the at least two input power sources into at least two rectified voltages. The switching switch switches one of the at least two rectified voltages. The determination circuit receives at least two power information, and determines at least two power supply status of the at least two input power sources according to the at least two power information to generate a determination signal. The switch control circuit receives the determination signal to generate a switch control signal to control the switching switch so as to switch one of the at least two rectification voltages.

Abstract: A test fixture assembly is for performing a test of a DUT (Device under Test), the DUT includes a plurality of pins exposed on a surface of the DUT, and the test fixture assembly includes a circuit board and a socket unit. The circuit board includes a plurality of test pads, which are exposed on a surface of the circuit board. The socket unit includes a socket base and a plurality of socket probes, which are inserted through the socket base. A first end and a second end of each of the socket probes are respectively exposed on two opposite surfaces of the socket base. Each of the test pads, a corresponding one of the socket probes and a corresponding one of the pins are configured to be linearly arranged along a socket probe direction.

Abstract: An antenna test assembly includes a DUT (Device under Test). The DUT includes an antenna module and a circuit board. The antenna module includes a first antenna element, which includes a first antenna pin and a second antenna pin. The circuit board includes a first line and a second line, and two ends of each of the first line and the second line are electrically connected to two metal pads, respectively, exposed on the circuit board. When the antenna test assembly is in an equipment test mode, the first line, the first antenna pin, the second antenna pin and the second line are electrically connected in sequence.

Abstract: A common-mode noise cancellation circuit includes a capacitor and an inductor. The inductor has a three coupled winding, including a first coupled winding, a second coupled winding, and a third coupled winding. An input end of the first coupled winding and an input end of the second coupled winding are respectively coupled to two ends of an input power source. An input end of the third coupled winding is coupled to the input end of the second coupled winding, and an output end of the third coupled winding is coupled to the capacitor. An output end of the first coupled winding and an output end of the second coupled winding are respectively coupled to two input ends of a power conversion stage.

Abstract: A common-mode noise cancellation circuit includes a capacitor and an inductor. The inductor has a three coupled winding, including a first coupled winding, a second coupled winding, and a third coupled winding. An input end of the first coupled winding and an input end of the second coupled winding are respectively coupled to two ends of an input power source. An input end of the third coupled winding is coupled to the output end of the second coupled winding, and an output end of the third coupled winding is coupled to the capacitor. An output end of the first coupled winding and an output end of the second coupled winding are respectively coupled to two input ends of a power conversion stage.

Abstract: A hybrid-mode power factor corrector includes a power factor correction circuit, a zero-crossing detection circuit, and a controller. The power factor correction circuit includes a power inductor and a power switch, and the zero-crossing detection circuit detects an inductor current. The controller controls the switching of the power switch by an operation frequency to control the power factor correction circuit converting an input voltage into an output voltage, and controls an input current drawn by the power factor correction circuit to follow the input voltage. The controller turns on the power switch to according to a switching time of the power switch when the power switch is switched to reach to the operation frequency and the inductor current is as low as a threshold value close to zero.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A multi-phase boost converting apparatus includes a multi-phase boost converter and a passive lossless snubber, wherein the passive lossless snubber includes a first resonant capacitor, a second resonant capacitor, an output-end first unidirectional conduction component, an output-end second unidirectional conduction component, an input-end first unidirectional conduction component, an input-end second unidirectional conduction component and a resonant inductor.

Abstract: A hybrid-mode power factor corrector includes a power factor correction circuit, a zero-crossing detection circuit, and a controller. The power factor correction circuit includes a power inductor and a power switch, and the zero-crossing detection circuit detects an inductor current. The controller controls the switching of the power switch by an operation frequency to control the power factor correction circuit converting an input voltage into an output voltage, and controls an input current drawn by the power factor correction circuit to follow the input voltage. The controller turns on the power switch to according to a switching time of the power switch when the power switch is switched to reach to the operation frequency and the inductor current is as low as a threshold value close to zero.

Abstract: An LLC resonant converting apparatus determines to operate as a half-bridge LLC resonant converter or a full-bridge LLC resonant converter based on the magnitude of the input voltage. The present disclosure can solve the problem that the input voltage range of the LLC resonant converter is not wide enough.

Abstract: The present invention provides a method for detecting a flash memory module and an associated SoC. The method reads data in a flash memory module with a specific data format, and then determining a plurality of characteristic parameters of the flash memory module and a size of a page by decoding and checking the data. Therefore, the SoC does not need to design a one-time-programmable memory or strap pins, so as to reduce the manufacturing cost of the SoC.

Abstract: A full-bridge phase-shift converter with voltage clamping includes a transformer, a primary-side circuit, and a secondary-side circuit. The secondary-side circuit includes a first synchronous rectifying switch, a second synchronous rectifying switch, an output inductor, a plurality of diodes, a capacitor, an energy-releasing unit, and an output capacitor. The capacitor provides a clamping voltage. The energy-releasing unit is coupled to the capacitor in parallel, and converts the clamping voltage into an output voltage. The output capacitor is coupled to the energy-releasing unit in parallel, and provides the output voltage.

Abstract: An electronic device includes a first case, a second case, and a locking assembly. The first case includes a first fixing surface, and the first fixing surface has a locking part. The second case includes a second fixing surface and two receiving grooves, and the two receiving grooves are respectively arranged on two sides of the second fixing surface. The locking assembly includes a buckle and two elastic elements. The buckle has a hook part and fixing rods. The fixing rods are arranged on two sides of the hook part. One end of each of the fixing rods abuts against the second fixing surface and slides relative to the second fixing surface, and another end of each of the fixing rods extends into the corresponding receiving groove. The hook part is configured to buckle to the locking part.