Abstract: A common-mode noise cancellation circuit includes a capacitor and an inductor. The inductor has a three coupled winding, including a first coupled winding, a second coupled winding, and a third coupled winding. An input end of the first coupled winding and an input end of the second coupled winding are respectively coupled to two ends of an input power source. An input end of the third coupled winding is coupled to the output end of the second coupled winding, and an output end of the third coupled winding is coupled to the capacitor. An output end of the first coupled winding and an output end of the second coupled winding are respectively coupled to two input ends of a power conversion stage.

Abstract: A common-mode noise cancellation circuit includes a capacitor and an inductor. The inductor has a three coupled winding, including a first coupled winding, a second coupled winding, and a third coupled winding. An input end of the first coupled winding and an input end of the second coupled winding are respectively coupled to two ends of an input power source. An input end of the third coupled winding is coupled to the input end of the second coupled winding, and an output end of the third coupled winding is coupled to the capacitor. An output end of the first coupled winding and an output end of the second coupled winding are respectively coupled to two input ends of a power conversion stage.

Abstract: A hybrid-mode power factor corrector includes a power factor correction circuit, a zero-crossing detection circuit, and a controller. The power factor correction circuit includes a power inductor and a power switch, and the zero-crossing detection circuit detects an inductor current. The controller controls the switching of the power switch by an operation frequency to control the power factor correction circuit converting an input voltage into an output voltage, and controls an input current drawn by the power factor correction circuit to follow the input voltage. The controller turns on the power switch to according to a switching time of the power switch when the power switch is switched to reach to the operation frequency and the inductor current is as low as a threshold value close to zero.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A multi-phase boost converting apparatus includes a multi-phase boost converter and a passive lossless snubber, wherein the passive lossless snubber includes a first resonant capacitor, a second resonant capacitor, an output-end first unidirectional conduction component, an output-end second unidirectional conduction component, an input-end first unidirectional conduction component, an input-end second unidirectional conduction component and a resonant inductor.

Abstract: A hybrid-mode power factor corrector includes a power factor correction circuit, a zero-crossing detection circuit, and a controller. The power factor correction circuit includes a power inductor and a power switch, and the zero-crossing detection circuit detects an inductor current. The controller controls the switching of the power switch by an operation frequency to control the power factor correction circuit converting an input voltage into an output voltage, and controls an input current drawn by the power factor correction circuit to follow the input voltage. The controller turns on the power switch to according to a switching time of the power switch when the power switch is switched to reach to the operation frequency and the inductor current is as low as a threshold value close to zero.

Abstract: An LLC resonant converting apparatus determines to operate as a half-bridge LLC resonant converter or a full-bridge LLC resonant converter based on the magnitude of the input voltage. The present disclosure can solve the problem that the input voltage range of the LLC resonant converter is not wide enough.

Abstract: The present invention provides a method for detecting a flash memory module and an associated SoC. The method reads data in a flash memory module with a specific data format, and then determining a plurality of characteristic parameters of the flash memory module and a size of a page by decoding and checking the data. Therefore, the SoC does not need to design a one-time-programmable memory or strap pins, so as to reduce the manufacturing cost of the SoC.

Abstract: A full-bridge phase-shift converter with voltage clamping includes a transformer, a primary-side circuit, and a secondary-side circuit. The secondary-side circuit includes a first synchronous rectifying switch, a second synchronous rectifying switch, an output inductor, a plurality of diodes, a capacitor, an energy-releasing unit, and an output capacitor. The capacitor provides a clamping voltage. The energy-releasing unit is coupled to the capacitor in parallel, and converts the clamping voltage into an output voltage. The output capacitor is coupled to the energy-releasing unit in parallel, and provides the output voltage.

Abstract: An electronic device includes a first case, a second case, and a locking assembly. The first case includes a first fixing surface, and the first fixing surface has a locking part. The second case includes a second fixing surface and two receiving grooves, and the two receiving grooves are respectively arranged on two sides of the second fixing surface. The locking assembly includes a buckle and two elastic elements. The buckle has a hook part and fixing rods. The fixing rods are arranged on two sides of the hook part. One end of each of the fixing rods abuts against the second fixing surface and slides relative to the second fixing surface, and another end of each of the fixing rods extends into the corresponding receiving groove. The hook part is configured to buckle to the locking part.

Abstract: A power supply used to convert an input voltage into an output voltage, and the power supply includes an input detection circuit, a conversion circuit, a detection circuit, and a controller. The input detection circuit provides a power good signal or a power fail signal according to the input voltage. The conversion circuit converts the input voltage into an output voltage, and the detection circuit detects the output voltage according to the power good signal to accordingly provide an output feedback signal with a first feedback value. The controller stabilizes a voltage level of the output voltage according to the first feedback value. The detection circuit self-adjusts a feedback condition according to the power fail signal, and correspondingly adjusts the output feedback signal to a second feedback value according to the feedback condition. The controller reduces the voltage level of the output voltage according to the second feedback value.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A multi-phase boost converting apparatus includes a multi-phase boost converter and a passive lossless snubber, wherein the passive lossless snubber includes a first resonant capacitor, a second resonant capacitor, an output-end first unidirectional conduction component, an output-end second unidirectional conduction component, an input-end first unidirectional conduction component, an input-end second unidirectional conduction component and a resonant inductor.

Abstract: An LLC resonant converting apparatus determines to operate as a half-bridge LLC resonant converter or a full-bridge LLC resonant converter based on the magnitude of the input voltage. The present disclosure can solve the problem that the input voltage range of the LLC resonant converter is not wide enough.

Abstract: A network communication power supply with digital signal isolation includes a transformer, a transformer drive circuit, a rectifier, and a modulation signal duty cycle detection circuit. The transformer has a primary side and a secondary side. The transformer drive circuit is coupled to the primary side, and receives a digital signal input. The transformer drive circuit converts the digital signal input into a drive signal with a duty cycle corresponding to a logic level of the digital signal input according to the logic level. The digital signal input includes a power content. The rectifier is coupled to the secondary side and converts the power content to provide a power source. The modulation signal duty cycle detection circuit is coupled to the rectifier and supplied power by the power source, and provides a digital signal output with a high or low level according to the duty cycle.

Abstract: A docking station and a control method thereof are provided. The docking station includes a first USB interface, a second USB interface, a video signal output terminal, a microcontroller, a first signal multiplexer, a second signal multiplexer, a video signal processor, and a video signal converter. The microcontroller determines whether the first USB interface or the second USB interface is connected to an electronic device. When the first USB interface is connected to the electronic device, the microcontroller sets the first USB interface as an uplink port. The uplink port receives a signal from the electronic device, and selects and outputs a video signal through the signal. The video signal processor is configured to receive and process the video signal. The video signal converter converts the video signal into a video output signal that is capable of being output to the video signal output terminal for playing.

Abstract: The invention provides a method for realizing a multi-channel convolutional recurrent neural network EEG emotion recognition model using transfer learning, the method uses a dual-channel one-dimensional convolutional neural network model constructed based on three heartbeats recognition method as the source domain model for transferring, to obtain a multi-channel convolutional recurrent neural network EEG emotion recognition model with EEG signal as the target domain, it solves the problem of scarcity of EEG labeling data, and can improve the accuracy of EEG emotion prediction.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A power supply used to convert an input voltage into an output voltage, and the power supply includes an input detection circuit, a conversion circuit, a detection circuit, and a controller. The input detection circuit provides a power good signal or a power fail signal according to the input voltage. The conversion circuit converts the input voltage into an output voltage, and the detection circuit detects the output voltage according to the power good signal to accordingly provide an output feedback signal with a first feedback value. The controller stabilizes a voltage level of the output voltage according to the first feedback value. The detection circuit self-adjusts a feedback condition according to the power fail signal, and correspondingly adjusts the output feedback signal to a second feedback value according to the feedback condition. The controller reduces the voltage level of the output voltage according to the second feedback value.