Abstract: The present disclosure provides a method and system for predicting a relative permeability curve based on machine learning. The present disclosure takes logging curve data as an input, and water saturation endpoint values as an output to establish a first relative permeability curve starting point model, and takes the logging curve data and a predicted water saturation starting value output from the first relative permeability curve starting point model as an input, and relative permeabilities under different water saturations as an output to establish a first relative permeability model, thereby obtaining a comprehensive prediction method for the relative permeability curve based on deep learning, and implying control mechanisms and parameters to a model.

Abstract: A driving backplane includes: a base; a first conductive layer disposed on the base, the first conductive layer including at least one first signal line; a first insulating layer disposed on a side of the first conductive layer away from the base; a second conductive layer disposed on a side of the first insulating layer away from the first conductive layer, the second conductive layer including at least one second signal line. Each first signal line and a second signal line constitute a signal line pair. In the signal line pair, extending directions of the first signal line and the second signal line are the same, an orthogonal projection of the first signal line on the base and an orthogonal projection of the second signal line on the base have a first overlapping region, and the second signal line is coupled to the first signal line.

Abstract: A method to initiate Command Address (CA) training on High Memory Bandwidth is provided to optimize CA bus setup and hold times relative to the memory clock. HBM protocol does not define any way to support CA training, but defines a very high working frequency. The high frequency makes it very difficult to ensure the timing on CA Bus-Row/Column command bus and CKE. As such, executing CA training before any normal operation is necessary to ensure the best setup/hold timings. The CA training takes advantage of protocol based instructions to initialize and implement CA training.

Abstract: Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.

Abstract: The present invention provides a vehicle-mounted device, a method for activating the vehicle-mounted device, and a vehicle-mounted system. The vehicle-mounted system includes a vehicle-mounted device, a data center, and a service platform. The vehicle-mounted device not only can be locally activated according to an activating information corresponding to an identity information of the vehicle-mounted device which indicates an unique identity of the vehicle-mounted device, but also can be remotely activated through wireless communication. Moreover, the vehicle-mounted system further includes application sub-modules which can provide extended/added functions. Therefore, by the method for activating a vehicle-mounted device provided by the present invention, the vehicle-mounted device can be activated in time, so that the information resources can be more easily and conveniently obtained by the user.

Abstract: The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.

Abstract: The present invention provides a intelligent data center based on a service platform for vehicle-mounted devices, including: a static data storage unit, adapted for storing static data relating to a vehicle-mounted device; a static data processing unit, adapted for processing the static data stored in the static data storage unit; a dynamic data storage unit, adapted for storing dynamic data which are relating to the vehicle-mounted device and acquired by the service platform for vehicle-mounted devices; and a data analysis unit, adapted for analyzing the static data and the dynamic data. The intelligent data center can provide a wide variety of services for the vehicle-mounted device through the service platform.

Abstract: A vehicle information system includes: a vehicle-mounted device, a network processing device and a service center which is adapted for providing service for the vehicle-mounted device. A service configuration channel is configured between the network processing device and the service center and is adapted for transmitting configuration data which are adapted for configuring service that is provided for the vehicle-mounted device. The service configuration channel is established on basis of connection to internet. A service channel system is configured between the vehicle-mounted device and the service center. A complete solution for providing information service may be provided by the vehicle information system, thereby improving the quality of user experience while using a vehicle.

Abstract: Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.

Abstract: Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.

Abstract: A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected to drains of the transistors, source lines at a second side of the gate electrodes, different from the first side, and connected to sources of the transistors on the semiconductor substrate, and charge storage regions between the gate electrodes and the floating bodies.

Abstract: A method of fabricating a nonvolatile memory device includes forming a tunnel insulating layer on a semiconductor substrate, forming a charge storage layer on the tunnel insulating layer, forming a dielectric layer on the charge storage layer, the dielectric layer including a first aluminum oxide layer, a silicon oxide layer, and a second aluminum oxide layer sequentially stacked on the charge storage layer, and forming a gate electrode on the dielectric layer, the gate electrode directly contacting the second aluminum oxide layer of the dielectric layer.

Abstract: A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected to drains of the transistors, source lines at a second side of the gate electrodes, different from the first side, and connected to sources of the transistors on the semiconductor substrate, and charge storage regions between the gate electrodes and the floating bodies.

Abstract: In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

Abstract: A method of fabricating a nonvolatile memory device includes forming a tunnel insulating layer on a semiconductor substrate, forming a charge storage layer on the tunnel insulating layer, forming a dielectric layer on the charge storage layer, the dielectric layer including a first aluminum oxide layer, a silicon oxide layer, and a second aluminum oxide layer sequentially stacked on the charge storage layer, and forming a gate electrode on the dielectric layer, the gate electrode directly contacting the second aluminum oxide layer of the dielectric layer.

Abstract: In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

Abstract: A charge trap flash memory device and method of making same are provided. The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.