Abstract: An apparatus for improving display quality of dynamic image on liquid crystal display (LCD) and a method thereof are provided. The apparatus includes an image data processing unit and an overdrive correcting unit. The overdrive correcting unit is coupled to the image data processing unit. The image data processing unit receives the image data and performs image processing. Then the image data processing unit stores the image data of previous frame after image processing. The overdrive correcting unit receives the image data of previous frame and current frame from the image data processing unit, and generates overdrive image data corresponding to the image data according to the image data of the previous frame and the image data of the current frame.

Abstract: A pulse extension circuit for extending a pulse signal includes an input unit for receiving the pulse signal, an edge detection unit coupled to the input unit for generating a initiation signal, a pulse initiation unit coupled to the edge detection unit for outputting a control signal and adjusting a voltage level of the control signal, a pulse width control unit coupled to the pulse initiation unit for outputting a termination signal, a reset unit coupled to the edge detection unit, the pulse initiation unit and the pulse width control unit for outputting the first reset signal and the second reset signal to reset the pulse initiation unit and the pulse width control unit, and an output unit coupled to the input unit and the pulse initiation unit for extending a signal period of the pulse signal according to the pulse signal and the control signal.

Abstract: A pulse extension circuit for extending a pulse signal includes an input unit for receiving the pulse signal, an edge detection unit coupled to the input unit for generating a initiation signal, a pulse initiation unit coupled to the edge detection unit for outputting a control signal and adjusting a voltage level of the control signal, a pulse width control unit coupled to the pulse initiation unit for outputting a termination signal, a reset unit coupled to the edge detection unit, the pulse initiation unit and the pulse width control unit for outputting the first reset signal and the second reset signal to reset the pulse initiation unit and the pulse width control unit, and an output unit coupled to the input unit and the pulse initiation unit for extending a signal period of the pulse signal according to the pulse signal and the control signal.

Abstract: A charge pump clock generating circuit and a method thereof are disclosed. The circuit includes a sync counter, a comparator, and a clock generating circuit. The sync counter receives a dot clock and a reset signal for accumulating a counting value according to the dot clock and resetting the counting value to a starting value when the reset signal is enabled. The comparator receives the counting value and outputs the reset signal when the counting value is greater than or equal to a preset value. The clock generating circuit receives a display clock and the reset signal and outputs a charge pump clock. The clock generating circuit transforms the logic state of the charge pump clock when the reset signal is enabled, and sets the charge pump clock to a first preset logic state when the display clock is transformed from a first state to a second state.

Abstract: A charge pump clock generating circuit and a method thereof are disclosed. The circuit includes a sync counter, a comparator, and a clock generating circuit. The sync counter receives a dot clock and a reset signal for accumulating a counting value according to the dot clock and resetting the counting value to a starting value when the reset signal is enabled. The comparator receives the counting value and outputs the reset signal when the counting value is greater than or equal to a preset value. The clock generating circuit receives a display clock and the reset signal and outputs a charge pump clock. The clock generating circuit transforms the logic state of the charge pump clock when the reset signal is enabled, and sets the charge pump clock to a first preset logic state when the display clock is transformed from a first state to a second state.

Abstract: “A charge pump used for producing at least a first output voltage and a second output voltage according to an input voltage is disclosed. The charge pump includes a pump unit, first to fourth switches, a first output capacitor and a second output capacitor. During a first period, the input voltage and a first voltage, through a first end and a second end of the pump unit respectively, charge at least an internal capacitor. During a second period, the internal capacitor, based on a second voltage level of the first switch and through the second switch, provides the first output capacitor with charges for producing the first output voltage. Finally, during a third period, the internal capacitor, based on a third voltage level of the third switch and through the fourth switch, provides the second output capacitor with charges for producing the second output voltage.

Abstract: A bus processing apparatus including a first buffer, a second buffer, an input control unit, an output control unit and a synchronous control unit is provided. The input control unit generates a storing address for deciding to output the transmitter data to either the first buffer or the second buffer according to a first timing and a data enable signal. The synchronous control unit receives and compares the storing address with a reading address in accordance with a second timing in order to output a data ready signal. The output control unit generates the reading address according to the second timing and the data ready signal, and reads the data stored in the first buffer or in the second buffer according to the reading address to output a receiver data to the receiver. Wherein, the frequency of second timing is not lower than the frequency of first timing.

Abstract: A charge pump used for producing at least a first output voltage and a second output voltage according to an input voltage is disclosed. The charge pump includes a pump unit, the first to fourth switches, a first output capacitor and a second output capacitor. During a first period, the input voltage and the first voltage, through the first end and the second end of the pump unit respectively, charge at least an internal capacitor. During a second period, the internal capacitor, based on the second voltage level of the first switch and though the second switch, provides the first output capacitor with charges for producing the first output voltage. Finally, during the third period, the internal capacitor, based on the third voltage level of the third switch and though the fourth switch, provides the second output capacitor with charges for producing the second output voltage.

Abstract: A process of effecting various anti compensation processes on input image on a plasma display panel comprises the steps of a) performing a gamma (i.e., ? equal to 0.45) compensation process on a video signal received by the PDP with respect to a ?; b) dividing the video signal into at least two segments based on a gray level thereof; and c) performing a variety of anti compensation processes on the video signal in respective segment. A smaller ? is used in the anti compensation process with respect to the video signal in a range of low gray level for increasing the gray level in the range of low gray level. Similarly, a larger ? is used in the anti compensation process with respect to the video signal in a range of high gray level for increasing a gradient in the range of high gray level, thereby obtaining a sharp image contrast, improving image quality, and rendering an enhanced image brightness.

Abstract: A method for implementing error diffusion on a plasma display panel (PDP) comprises the steps of performing an anti compensation process on a received video signal of the PDP; diffusing an error generated by a first one of a plurality of pixels to a plurality of adjacent pixels; absorbing errors generated by the plurality of adjacent pixels by the first pixel; and multiplying each of a plurality of numeric weightings and the error of each of the adjacent pixels to obtain an error function of the first pixel. This is effected in a cost effective while simple addition circuit for solving the problem of low level contouring in PDP due to insufficient gray scale of video signal in low gray scale.

Abstract: A method for reducing dynamic false contour in a plasma display panel (PDP) comprising the steps of selecting gray scales of different visual concentration series from all of gray scales available to be shown on said PDP to form a visual concentration conversion table, selecting at least one of said visual concentration series as a virtual visual concentration series, and converting original input value of gray scale of each discharge unit into corresponding gray scales of different visual concentration series and virtual visual concentration series, while showing each field of a dynamic image on said PDP, in order to average visual concentration difference between gray scales of two adjacent discharge units on the dynamic field into a smaller one.

Abstract: A method for reducing dynamic false contour in a plasma display panel (PDP) comprising the steps of selecting gray scales of different visual concentration series from all of gray scales available to be shown on said PDP to form a visual concentration conversion table, selecting at least one of said visual concentration series as a virtual visual concentration series, and converting original input value of gray scale of each discharge unit into corresponding gray scales of different visual concentration series and virtual visual concentration series, while showing each field of a dynamic image on said PDP, in order to average visual concentration difference between gray scales of two adjacent discharge units on the dynamic field into a smaller one.

Abstract: A method for implementing error diffusion on a plasma display panel (PDP) comprises the steps of performing an anti compensation process on a received video signal of the PDP; diffusing an error generated by a first one of a plurality of pixels to a plurality of adjacent pixels; absorbing errors generated by the plurality of adjacent pixels by the first pixel; and multiplying each of a plurality of numeric weightings and the error of each of the adjacent pixels to obtain an error function of the first pixel. This is effected in a cost effective while simple addition circuit for solving the problem of low level contouring in PDP due to insufficient gray scale of video signal in low gray scale.

Abstract: A process of effecting various anti compensation processes on input image on a plasma display panel comprises the steps of a) performing a gamma (i.e., &ggr; equal to 0.45) compensation process on a video signal received by the PDP with respect to a &ggr;; b) dividing the video signal into at least two segments based on a gray level thereof; and c) performing a variety of anti compensation processes on the video signal in respective segment. A smaller &ggr; is used in the anti compensation process with respect to the video signal in a range of low gray level for increasing the gray level in the range of low gray level. Similarly, a larger &ggr; is used in the anti compensation process with respect to the video signal in a range of high gray level for increasing a gradient in the range of high gray level, thereby obtaining a sharp image contrast, improving image quality, and rendering an enhanced image brightness.