Abstract: Embodiments of present disclosure relates to forming isolation structures in gate structures to prevent current leakage through source/drain regions (EPI), transistors, and silicon substrate. The isolation structures are arranged in a pattern with a long isolation structure adjacent a short isolation structure. The isolation structures may be formed in the gate structure prior to or after the replacement gate sequence.

Abstract: The present invention relates to a novel antibody, an antigen-binding fragment thereof and the uses of the antibody and fragment, wherein the antibody and the fragment comprise specific complementarity-determining regions (CDRs) and/or specifically bind to human CD73 at specific epitopes.

Abstract: A structure includes a plurality of semiconductor regions, a first gate stack and a second gate stack immediately neighboring each other, a first fin isolation region in the first gate stack, and a second fin isolation region in the second gate stack. The first fin isolation region and the second fin isolation region have a sideway overlap having an overlap distance being equal to or greater than a pitch of the plurality of semiconductor regions. The overlap distance is measured in a direction parallel to lengthwise directions of the first gate stack and the second gate stack. A plurality of source/drain regions are on opposing sides of the first gate stack and the second gate stack to form a plurality of transistors.

Abstract: Methods for isolating two adjacent transistors are disclosed. A substrate has a first semiconducting fin on a first region and a second semiconducting fin on a second region, and the first semiconducting fin and the second semiconducting fin contact each other at a jog region. A dummy gate within or adjacent the jog region is removed to expose a portion of the first semiconducting fin and form an isolation volume. Etching is performed to remove the exposed portion of the first semiconducting fin and create a trench in the substrate. The trench and the isolation volume are filled with at least one dielectric material to form an electrically isolating structure between the first region and the second region. Additional dummy gates in each region can be removed and replaced with an electrically conductive material to form two adjacent transistors electrically isolated from each other.

Abstract: A continuous metal on diffusion edge (CMODE) may be used to form a CMODE structure in a semiconductor device after a replacement gate process that is performed to replace the polysilicon dummy gate structures of the semiconductor device with metal gate structures. The CMODE process described herein includes removing a portion of a metal gate structure (as opposed to removing a portion of a polysilicon dummy gate structure) to enable formation of the CMODE structure in a recess left behind by removal of the portion of the metal gate structure.

Abstract: Methods for fabricating semiconductor devices are provided. An exemplary method includes forming fins in a dense region and in an isolated region of a semiconductor substrate; performing a plasma dry etch process to remove a portion of at least one selected fin to form a first trench in the dense region and to remove a portion of at least one selected fin in the isolated region to form a second trench in the isolated region, wherein the plasma dry etch process includes: performing a passivation-oriented process and an etchant-oriented process; and controlling the passivation-oriented process and the etchant-oriented process to form the first trench with a desired first critical dimension and first depth and to form the second trench with a desired second critical dimension and second depth.

Abstract: The present invention relates to a novel antibody, an antigen-binding fragment thereof and the uses of the antibody and fragment, wherein the antibody and the fragment comprise specific complementarity-determining regions (CDRs) and/or specifically bind to human CD73 at specific epitopes.

Abstract: Devices with metal structures formed with seams and methods of fabrication are provided. An exemplary method includes forming a metal plug having a top surface formed with a seam; depositing a film over the top surface of the metal plug and at least partially filling the seam; and etching the film from over the metal plug, wherein the film remains in the seam.

Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

Abstract: Provided are semiconductor devices with isolation structures and methods for fabricating such devices. An exemplary method includes forming an isolation layer over a semiconductor material; forming source/drain regions over the isolation layer; removing a selected gate structure, wherein removing the selected gate structure forms a trench in the semiconductor material; and forming an isolation structure in the trench.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a first fin and around first channel regions that are disposed over the first fin; forming an interlayer dielectric (ILD) layer over the first fin around the dummy gate structure; replacing the dummy gate structure with a gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposing sides of the first fin, where the first and second dielectric plugs cut the gate structure into a plurality of segments separated from each other; removing a segment of the gate structure interposed between the first dielectric plug and the second dielectric plugs to expose the first channel regions; removing the exposed first channel regions, where after removing the exposed first channel regions, a recess is formed in the ILD layer; and filling the recess with a dielectric material.

Abstract: A humanized anti-neurotensin receptor 1 (NTSR1) antibody or an antigen-binding fragment thereof. Also, a method for treating, prophylactic treating and/or preventing diseases and/or disorders caused by or related to NTSR1 activity and/or signaling, and a method or kit for detecting NTSR1 in a sample.

Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

Abstract: A circuit board for a semiconductor testing includes first and second substrates, first and second insulating dielectric layers attached to the lower surface of the first substrate and the upper surface of the second substrate respectively and attached to each other, and electrically conductive fillers disposed in first and second through holes of the first and second insulating dielectric layers and electrically connected with first and second electrically conductive pads of the first and second substrates. For the first through holes, compared with the upper ends thereof, the lower ends thereof have larger width or smaller interval. For the second through holes, compared with the lower ends thereof, the upper ends thereof have larger width or smaller interval. A method of manufacturing the circuit board is also disclosed. Accordingly, an alignment problem in connecting substrates by the insulating dielectric layer may be improved, thereby enhancing the circuit integrity.

Abstract: An antibody, or an antigen-binding fragment thereof, that binds specifically to human CSF-1R includes a heavy chain variable domain that contains a HCDR1 region having the sequence of SEQ ID NO: 4, a HCDR2 region having the sequence of SEQ ID NO: 5, and a HCDR3 region having the sequence of SEQ ID NO: 6; and a light chain variable domain that contains a LCDR1 region having the sequence of SEQ ID NO: 7, a LCDR2 region having the sequence of SEQ ID NO: 8, and a LCDR3 region having the sequence of SEQ ID NO: 9. The heavy chain variable domain comprises the sequence of SEQ ID NO: 2, and wherein the light chain variable domain comprises the sequence of SEQ ID NO: 3.

Abstract: A humanized anti-neurotensin receptor 1 (NTSR1) antibody or an antigen-binding fragment thereof. Also, a method for treating, prophylactic treating and/or preventing diseases and/or disorders caused by or related to NTSR1 activity and/or signaling, and a method or kit for detecting NTSR1 in a sample.

Abstract: The present disclosure relates to an anti-PD-L1 antibody or an antigen-binding fragment thereof, comprising: a heavy chain variable region sequence comprising the three CDRs with the sequences of SEQ ID NOs: 2 to 4, or 6 to 8; and a light chain variable region sequence comprising the three CDRs with the sequences of SEQ ID NOs: 10 to 12, or 14 to 16. The present disclosure also relates to a pharmaceutical composition and a method for detecting expression of PD-L1 in a sample.

Abstract: The present disclosure provides an immunoconjugate includes an antibody comprising an antigen-binding fragment that specifically binds to an epitope in mesothelin, N-glycan binding domain and an N-glycan; a linker linking to the N-glycan; and a payload A and a payload B conjugated to the linker, respectively; wherein the payload A and the payload B are the same or different. A pharmaceutical composition comprises the immunoconjugate and a method for treating cancer are also provided in the disclosure.

Abstract: A system and a method for parameter optimization with adaptive search space and a user interface using the same are provided. The system includes a data acquisition unit, an adaptive adjustment unit and an optimization search unit. The data acquisition unit obtains a set of executed values of several operating parameters and a target parameter. The adaptive adjustment unit includes a parameter space transformer and a search range definer. The parameter space transformer performs a space transformation on a parameter space of the operating parameters according to the executed values. The search range definer defines a parameter search range in a transformed parameter space based on the sets of the executed values. The optimization search unit takes the parameter search range as a limiting condition and takes optimizing the target parameter as a target to search for a set of recommended values of the operating parameters.

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.