Patents by Inventor Liang Min

Liang Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11914937
    Abstract: Techniques, systems, and devices are described for providing a computational frame for estimating high-dimensional stochastic behaviors. In one exemplary aspect, a method for performing numerical estimation includes receiving a set of measurements of a stochastic behavior. The set of correlated measurements follows a non-standard probability distribution and is non-linearly correlated. Also, a non-linear relationship exists between a set of system variables that describes the stochastic behavior and a corresponding set of measurements. The method includes determining, based on the set of measurements, a numerical model of the stochastic behavior. The numerical model comprises a feature space comprising non-correlated features corresponding to the stochastic behavior. The non-correlated features have a dimensionality of M and the set of measurements has a dimensionality of N, M being smaller than N.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: February 27, 2024
    Assignees: LAWRENCE LIVERMORE NATIONAL SECURITY, LLC, VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.
    Inventors: Xiao Chen, Can Huang, Liang Min, Charanraj Thimmisetty, Charles Tong, Yijun Xu, Lamine Mili
  • Publication number: 20230205955
    Abstract: Techniques, systems, and devices are described for providing a computational frame for estimating high-dimensional stochastic behaviors. In one exemplary aspect, a method for performing numerical estimation includes receiving a set of measurements of a stochastic behavior. The set of correlated measurements follows a non-standard probability distribution and is non-linearly correlated. Also, a non-linear relationship exists between a set of system variables that describes the stochastic behavior and a corresponding set of measurements. The method includes determining, based on the set of measurements, a numerical model of the stochastic behavior. The numerical model comprises a feature space comprising non-correlated features corresponding to the stochastic behavior. The non-correlated features have a dimensionality of M and the set of measurements has a dimensionality of N, M being smaller than N.
    Type: Application
    Filed: February 13, 2023
    Publication date: June 29, 2023
    Inventors: Xiao Chen, Can Huang, Liang Min, Charanraj Thimmisetty, Charles Tong, Yijun Xu, Lamine Mili
  • Patent number: 11580280
    Abstract: Techniques, systems, and devices are described for providing a computational frame for estimating high-dimensional stochastic behaviors. In one exemplary aspect, a method for performing numerical estimation includes receiving a set of measurements of a stochastic behavior. The set of correlated measurements follows a non-standard probability distribution and is non-linearly correlated. Also, a non-linear relationship exists between a set of system variables that describes the stochastic behavior and a corresponding set of measurements. The method includes determining, based on the set of measurements, a numerical model of the stochastic behavior. The numerical model comprises a feature space comprising non-correlated features corresponding to the stochastic behavior. The non-correlated features have a dimensionality of M and the set of measurements has a dimensionality of N, M being smaller than N.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: February 14, 2023
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Xiao Chen, Can Huang, Liang Min, Charanraj Thimmisetty, Charles Tong
  • Patent number: 11496143
    Abstract: Smart electric meters configured to perform fast, time-synchronized electrical energy measurements at the consumer-level are disclosed herein. In some embodiments, a smart electric meter includes circuitry configured to measure an electrical value at a location of an end user in a power system. The smart electric meter can further include an atomic clock configured to output a timing signal, and a controller configured to receive (a) the measured electrical value from the circuitry and (b) the timing signal from the atomic clock. The controller can further (a) process the electrical value to generate meter data and (b) generate a time tag based on the timing signal. Then, the controller can associate the time tag with the meter data to generate time-tagged meter data.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: November 8, 2022
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Liang Min, Can Huang
  • Publication number: 20210191946
    Abstract: Systems and methods of monitoring for anomalous data records. The system conducts a method including: receiving a data record associated with at least one meta attribute to determine whether subsequent processing of the data record is warranted; generating an anomaly prediction for the data record based on a detection model and the at least one meta attribute associated with the data record, the detection model defined by a plurality of score distribution representations based on quantile bins and a dynamic quantile weight for providing an interim anomaly measure corresponding to respective score distribution representations, wherein the anomaly prediction is generated based on a combination of interim anomaly measures associated with respective meta attributes associated with the data record; and transmitting a signal representing the anomaly prediction for presentation at a user device for identifying one or more data records for subsequent data processes.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 24, 2021
    Inventors: Kanika VIJ, Igor RESHYNSKY, Harneet JASSAL, Emma HU, Liang MIN, Adam LAZURE, Esther CHOI, Rowan COMISH, Jingyi GAO, Leung GLADYS, Diane FENTON
  • Publication number: 20210135677
    Abstract: Smart electric meters configured to perform fast, time-synchronized electrical energy measurements at the consumer-level are disclosed herein. In some embodiments, a smart electric meter includes circuitry configured to measure an electrical value at a location of an end user in a power system. The smart electric meter can further include an atomic clock configured to output a timing signal, and a controller configured to receive (a) the measured electrical value from the circuitry and (b) the timing signal from the atomic clock. The controller can further (a) process the electrical value to generate meter data and (b) generate a time tag based on the timing signal. Then, the controller can associate the time tag with the meter data to generate time-tagged meter data.
    Type: Application
    Filed: August 7, 2020
    Publication date: May 6, 2021
    Inventors: Liang Min, Can Huang
  • Publication number: 20210055334
    Abstract: Systems and methods for voltage stability monitoring and active/reactive power support are disclosed herein. In some embodiments, a smart electric meter of an end user in a grid power system can measure the voltage supplied to the end user via the grid power system, and can analyze the voltage data to detect critical voltage characteristics. The critical voltage characteristics may indicate that a voltage collapse event is likely. The smart electric meter can further estimate a voltage stability margin based on the voltage data. If necessary, the smart electric meter can control an electrical power source and/or an electric appliance positioned at or near the end user to increase the voltage stability margin.
    Type: Application
    Filed: August 19, 2020
    Publication date: February 25, 2021
    Inventors: Liang Min, Nan Duan
  • Publication number: 20200202057
    Abstract: Techniques, systems, and devices are described for providing a computational frame for estimating high-dimensional stochastic behaviors. In one exemplary aspect, a method for performing numerical estimation includes receiving a set of measurements of a stochastic behavior. The set of correlated measurements follows a non-standard probability distribution and is non-linearly correlated. Also, a non-linear relationship exists between a set of system variables that describes the stochastic behavior and a corresponding set of measurements. The method includes determining, based on the set of measurements, a numerical model of the stochastic behavior. The numerical model comprises a feature space comprising non-correlated features corresponding to the stochastic behavior. The non-correlated features have a dimensionality of M and the set of measurements has a dimensionality of N, M being smaller than N.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 25, 2020
    Inventors: Xiao Chen, Can Huang, Liang Min, Charanraj Thimmisetty, Charles Tong
  • Patent number: 9786441
    Abstract: The instant disclosure provides a solid electrolytic capacitor package structure and method of manufacturing the same. The solid electrolytic capacitor package structure includes a capacitor assembly, at least one electrode pin and a package body enclosing the capacitor assembly and the electrode pin. The electrode pin includes an embedded portion enclosed by the package body and an exposed portion positioned outside the package body. The method of manufacturing the solid electrolytic capacitor package structure includes a protection step including forming a protecting film on the exposed portion; a coating step including depositing a nanomaterial on the solid electrolytic capacitor package structure to form a nanofilm, wherein the nanomaterial penetrates into defects of the solid electrolytic capacitor package structure; and a deprotection step including removing the protecting film.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: October 10, 2017
    Assignee: APAQ TECHNOLOGY CO., LTD.
    Inventors: Ching-Feng Lin, Liang-Min Kao, Chun-Chia Huang
  • Publication number: 20170110256
    Abstract: The instant disclosure provides a solid electrolytic capacitor package structure and method of manufacturing the same. The solid electrolytic capacitor package structure includes a capacitor assembly, at least one electrode pin and a package body enclosing the capacitor assembly and the electrode pin. The electrode pin includes an embedded portion enclosed by the package body and an exposed portion positioned outside the package body. The method of manufacturing the solid electrolytic capacitor package structure includes a protection step including forming a protecting film on the exposed portion; a coating step including depositing a nanomaterial on the solid electrolytic capacitor package structure to form a nanofilm, wherein the nanomaterial penetrates into defects of the solid electrolytic capacitor package structure; and a deprotection step including removing the protecting film.
    Type: Application
    Filed: May 5, 2016
    Publication date: April 20, 2017
    Inventors: CHING-FENG LIN, LIANG-MIN KAO, CHUN-CHIA HUANG
  • Publication number: 20170082687
    Abstract: A method performed on a user interface device is described. The method includes connecting to a smart card where the smart card is connected to an electronic system to be de-bugged. The method also includes causing a cloud service to download customized test vectors for the electronic system to the smart card. The method also includes causing the smart card to begin execution of test software and/or operation of programmable hardware logic circuitry that uses the customized test vectors to test the electronic system.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventors: ROLAND W. KLINGER, DIRK F. BLEVINS, JOHN M. MORGAN, ERIC D. HEATON, AI BEE LIM, LIANG-MIN WANG
  • Patent number: 9361233
    Abstract: An apparatus and method for implementing a shared unified cache. For example, one embodiment of a processor comprises: a plurality of processor cores grouped into modules, wherein each module has at least two processor cores grouped therein; a plurality of level 1 (L1) caches, each L1 cache directly accessible by one of the processor cores; a level 2 (L2) cache associated with each module, the L2 cache directly accessible by each of the processor cores associated with its respective module; a shared unified cache to store data and/or instructions for each of the processor cores in each of the modules; and a cache management module to manage the cache lines in the shared unified cache using a first cache line eviction policy favoring cache lines which are shared across two or more modules and which are accessed relatively more frequently from the modules.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 7, 2016
    Assignee: INTEL CORPORATION
    Inventors: Liang-Min Wang, John M. Morgan, Namakkal N. Venkatesan
  • Publication number: 20150178199
    Abstract: An apparatus and method for implementing a shared unified cache. For example, one embodiment of a processor comprises: a plurality of processor cores grouped into modules, wherein each module has at least two processor cores grouped therein; a plurality of level 1 (L1) caches, each L1 cache directly accessible by one of the processor cores; a level 2 (L2) cache associated with each module, the L2 cache directly accessible by each of the processor cores associated with its respective module; a shared unified cache to store data and/or instructions for each of the processor cores in each of the modules; and a cache management module to manage the cache lines in the shared unified cache using a first cache line eviction policy favoring cache lines which are shared across two or more modules and which are accessed relatively more frequently from the modules.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Inventors: Liang-Min Wang, John M. Morgan, Namakkal N. Venkatesan
  • Patent number: 8650425
    Abstract: A computer system for processing data in a non-operational state and processing method thereof are provided. The computer system includes a data output unit, a data source, a data processing module and a state monitor unit. The data processing module accesses and processes data from the data source, and transmits the processed data to the data output unit. The state monitor unit monitors a power supply state of the computer system to generate a state switch signal, which indicates whether the computer system is in an operational state or a non-operational state. When the state switch signal indicates that the computer system is in a non-operational state, the data source and the data processing module receives operating voltages to access and process data.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: February 11, 2014
    Assignee: Via Technologies, Inc.
    Inventors: Chung-Ching Huang, Yeh Cho, Kuo-Han Chang, Liang-Min Lee, Donna Lim
  • Publication number: 20130297951
    Abstract: An operation system including a chipset and a detection unit is disclosed. The chipset includes a first circuit group receiving a plurality of operation voltages. The detection unit generates a control signal to control the first circuit group to stop accessing a memory device when an external power is abnormal. A level of the control signal switches before variation in a level of a first operation voltage among the operation voltages. The variation is induced when the external power is abnormal.
    Type: Application
    Filed: August 9, 2012
    Publication date: November 7, 2013
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Liang Min LEE, Chia-Hung SU, Hung-Yi KUO, Yu Jen CHANG
  • Patent number: 8126667
    Abstract: A measurement base voltage stability monitoring and control scheme having a means for measuring current and voltage phasors at a boundary bus of a load center; and an equivalent network having a fictitious bus with an aggregate load representative of all loads of the load center. The scheme further includes a computing device to calculate a voltage stability margin index based on the aggregate load of the fictitious bus and compare the voltage stability margin index to a pre-set threshold. The computing device causes an action to take place based on the comparison between the voltage stability margin index and the pre-set threshold.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: February 28, 2012
    Assignee: Electric Power Research Institute, Inc.
    Inventors: Pei Zhang, Liang Min, Jian Chen
  • Publication number: 20120044079
    Abstract: A measurement base voltage stability monitoring and control scheme having a means for measuring current and voltage phasors at a boundary bus of a load center; and an equivalent network having a fictitious bus with an aggregate load representative of all loads of the load center. The scheme further includes a computing device to calculate a voltage stability margin index based on the aggregate load of the fictitious bus and compare the voltage stability margin index to a pre-set threshold. The computing device causes an action to take place based on the comparison between the voltage stability margin index and the pre-set threshold.
    Type: Application
    Filed: November 2, 2011
    Publication date: February 23, 2012
    Applicant: ELECTRIC POWER RESEARCH INSTITUTE, INC.
    Inventors: Pei Zhang, Liang Min, Jian Chen
  • Publication number: 20120041611
    Abstract: A measurement base voltage stability monitoring and control scheme having a means for measuring current and voltage phasors at a boundary bus of a load center; and an equivalent network having a fictitious bus with an aggregate load representative of all loads of the load center. The scheme further includes a computing device to calculate a voltage stability margin index based on the aggregate load of the fictitious bus and compare the voltage stability margin index to a pre-set threshold. The computing device causes an action to take place based on the comparison between the voltage stability margin index and the pre-set threshold.
    Type: Application
    Filed: October 25, 2011
    Publication date: February 16, 2012
    Applicant: ELECTRIC POWER RESEARCH INSTITUTE, INC.
    Inventors: Pei Zhang, Liang Min, Jian Chen
  • Publication number: 20100287395
    Abstract: A computer system for processing data in a non-operational state and processing method thereof are provided. The computer system includes a data output unit, a data source, a data processing module and a state monitor unit. The data processing module accesses and processes data from the data source, and transmits the processed data to the data output unit. The state monitor unit monitors a power supply state of the computer system to generate a state switch signal, which indicates whether the computer system is in an operational state or a non-operational state. When the state switch signal indicates that the computer system is in a non-operational state, the data source and the data processing module receives operating voltages to access and process data.
    Type: Application
    Filed: May 5, 2010
    Publication date: November 11, 2010
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Chung-Ching Huang, Yeh Cho, Kuo-Han Chang, Liang-Min Lee, Donna Lim
  • Publication number: 20090299664
    Abstract: A measurement base voltage stability monitoring and control scheme having a means for measuring current and voltage phasors at a boundary bus of a load center; and an equivalent network having a fictitious bus with an aggregate load representative of all loads of the load center. The scheme further includes a computing device to calculate a voltage stability margin index based on the aggregate load of the fictitious bus and compare the voltage stability margin index to a pre-set threshold. The computing device causes an action to take place based on the comparison between the voltage stability margin index and the pre-set threshold.
    Type: Application
    Filed: June 3, 2008
    Publication date: December 3, 2009
    Applicant: ELECTRIC POWER RESEARCH INSTITUTE, INC.
    Inventors: Pei Zhang, Liang Min, Jian Chen