Abstract: The present disclosure provides a semi-physical simulation test bench and test method for a multi-machine parallel operation device of gas turbines. The gas turbines are all connected with gearbox shafts through SSS clutches, torque meters and couplers, and then a hydraulic dynamometer, an electric turbine dynamometer and a generator are independently or jointly driven through couplers and torque meters so as to charge a storage battery. Multi-shaft gearboxes comprise parallel operation gearboxes, and are connected with a bridging gearbox through couplers, electromagnetic clutches, supports, torque meters and couplers. The gas turbines can drive an electric dynamometer and the electric turbine dynamometer independently or cooperatively, so that the system has good operation characteristics under different working conditions. Meanwhile, the storage battery is additionally arranged, the flexibility of the test bench is improved, and the energy utilization rate is increased.

Abstract: A smart thermostatic system is disclosed that applies one or more of a reinforcement and/or adaptive learning model for a new environment with the trained model from another environment so as to initiate status of a thermostatic device. In one example, the thermostatic system uses a pretrained machine learning model that is transferred from a first thermostatic system to a second thermostatic system in a similar sub-environment. Temperature data and other data collected by the thermostatic device is used to fine-tune and train the pretrained model to learn, predict, and better adjust the operation of the thermostatic system.

Abstract: A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.

Abstract: A power apparatus includes a substrate, a first power circuit, and a second power circuit. The substrate includes a first metallization region, a second metallization region, and a third metallization region which are separated from each other. The first power circuit is electrically connected to the first metallization region and the third metallization region, and is arranged across the second metallization region and fails to be in contact with the second metallization region. The second power circuit is electrically connected to the second metallization region and the third metallization region, and fails to be in contact with the first metallization region.

Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.

Abstract: Systems and methods of the various embodiments may provide a battery including a rolling diaphragm configured to move to accommodate an internal volume change of one or more components of the battery. Systems and methods of the various embodiments may provide a battery housing including a rolling diaphragm seal disposed between an interior volume of the battery and an electrode assembly within the battery. Various embodiments may provide an air electrode assembly including an air electrode supported on a buoyant platform such that the air electrode is above a surface of a volume of electrolyte when the buoyant platform is floating in the electrolyte.

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: According to one aspect, an electrochemical cell may include a positive electrode, a negative electrode, and an electrolyte separating the positive electrode and the negative electrode from one another. The positive electrode, the negative electrode, and the electrolyte may collectively store and discharge energy by an electrode reaction of chlorine dioxide (ClO2).

Abstract: An electrochemical cell and battery system including cells, each cell including a catholyte, an anolyte, and a separator disposed between the catholyte and anolyte and that is permeable to the at least one ionic species (for example, a metal cation or the hydroxide ion). The catholyte solution includes a ferricyanide, permanganate, manganate, sulfur, and/or polysulfide compound, and the anolyte includes a sulfide and/or polysulfide compound. These electrochemical couples may be embodied in various physical architectures, including static (non-flowing) architectures or in flow battery (flowing) architectures.

Abstract: A method of forming a semiconductor structure includes the following operations. A semiconductor epitaxial layer is formed on a first semiconductor substrate. A first side of the semiconductor epitaxial layer is adhered to a transfer substrate by an adhesive layer covering the first side of the semiconductor epitaxial layer. The semiconductor epitaxial layer and the first semiconductor substrate are turned over by the transfer substrate. The first semiconductor substrate is removed to expose a second side of the semiconductor epitaxial layer opposite to the first side. A first semiconductor doped region is formed on the second side of the semiconductor epitaxial layer. After the first semiconductor doped region is formed, the adhesive layer and the transfer substrate are removed.

Abstract: A routing information management method adapted for a layer-3 switch is proposed. For each ARP entry in an ARP table, a processor assigns to the ARP entry an aging reference parameter that is identical to a quantity of those routing entries in an IP routing table whose next hop IP addresses are identical to the IP address of the ARP entry, and removes those ARP entries whose aging reference parameters are zero. For each routing entry in the IP routing table, when the next hop IP address of the routing entry is absent from the ARP table, the processor makes the routing entry serve as an inactive routing entry, proactively sends an ARP request for the inactive routing entry, and updates the ARP table based on a piece of ARP information received externally.

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.

Abstract: A method includes implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; forming a transistor structure on a front side of the semiconductor substrate; forming a front-side interconnect structure over the transistor structure; performing a thinning process on a back side of the semiconductor substrate to reduce a thickness of the semiconductor substrate, wherein the thinning process is slowed by the etch stop region; and forming a back-side interconnect structure over the back side of the semiconductor substrate.

Abstract: A cloud platform provides a cloud phone configuration interface for a user to configure a template cloud phone based on a first input of the user. The cloud platform then provides a network shared file configuration interface for the user to store a directory of the template cloud phone into a first network shared file based on a second input of the user, and then configure, based on a third input of the user, at least one to-be-configured cloud phone to mount the first network shared file, to complete installation of a plurality of applications. Therefore, the cloud phone installs, updates, and uninstalls the applications by mounting the network shared file.

Abstract: A Bacillus altitudinis ST15 antagonizing Xanthomonas oryzae and use thereof, the Bacillus altitudinis ST15 was deposited in China General Microbiological Culture Collection Center on Jun. 28, 2020 and has the deposit number of CGMCC No. 20156. The Bacillus altitudinis has a relatively high antagonistic activity to Xanthomonas oryzae pv. oryzae and Xanthomonas oryzae pv. oryzicola, can promote growth of rice and improve a drought resistance of a rice seedling, and has a relatively strong tolerance to common chemical microbicides for controlling bacterial diseases of rice. A bacterial suspension or a biocontrol inoculant prepared from this strain has a relatively high biocontrol effect on bacterial blight of rice and bacterial leaf streak of rice, can replace or reduce chemical pesticides, improves safety of food and ecological environment, and has relatively high economic and social benefits.

Abstract: A hierarchy of controls and parts, that are each in accordance with constraints of a computing executing context. A control is executable code that performs a function and which may impart a visualization. A part is a unit of visualization container that has its own visualization and/or shows visualizations from one or more compliant controls associated with the part.

Abstract: Aspects of the subject matter described herein relate to publishing applications from a source environment to a target environment. In aspects, a publishing pipeline has multiple segments in which work related to the publishing is performed. In the pipeline, file data associated with an application is collected. Settings that need to be created and/or changed in target environment are also determined. Transformation actions may also occur to determine and prepare files to be published to the target environment. After the files and settings to publish are determined and the transformation actions occur, the application may then be published to the target environment.

Abstract: A touch pen comprises a penholder, an electrically conducting core, a flexible covering and fabric covering. The electrically conducting core is coupled to the penholder. The electrically conducting core is ensheathed in the flexible covering, while the fabric covering wraps around the flexible covering, wherein either flexible covering or fabric covering has electrical conductivity. In the present invention, the flexible covering and the fabric covering are shaped under the pressure exerted by the electrically conducting core and a touch panel so as to increase the contact area between the touch pen and the touch panel and, meanwhile, the fabric covering is capable of reducing the friction between touch pen and the touch panel, thereby improving the sensitivity and touch effect.

Abstract: Aspects of the subject matter described herein relate to publishing applications from a source environment to a target environment. In aspects, a publishing pipeline has multiple segments in which work related to the publishing is performed. In the pipeline, file data associated with an application is collected. Settings that need to be created and/or changed in target environment are also determined. Transformation actions may also occur to determine and prepare files to be published to the target environment. After the files and settings to publish are determined and the transformation actions occur, the application may then be published to the target environment.

Abstract: A method for driving a tri-gate TFT-LCD includes providing a polarity converting common voltage. When polarity of the common voltage is converted, a first gate line is turned on for a source line to charge a first sub-pixel for a first write in duration. When the first gate line is turned off, a second gate line is turned on for the source line to charge a second sub-pixel for a second write in duration. When the second gate line is turned off, a third gate line is turned on for the source line to charge a third sub-pixel for the second write in duration. By adjusting the first write in duration the first sub-pixel can be fully charged, consequently improving the color deviation of the displayed image.