Abstract: A semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a plurality of drain regions in a substrate; a plurality of capacitor plugs on the plurality of drain regions; a plurality of lower electrodes on the plurality of capacitor plugs and respectively including a U-shaped cross-sectional profile; a lower supporting layer above the substrate, against on outer surfaces of the plurality of lower electrodes, and including: a plurality of first openings along the lower supporting layer and between the plurality of lower electrodes; and a higher supporting layer above the lower supporting layer, against on the outer surfaces of the plurality of lower electrodes, and including a plurality of second openings along the higher supporting layer and topographically aligned with the plurality of first openings. The widths of the first openings and the widths of the second openings are substantially the same.

Abstract: A semiconductor device includes a plurality of drain regions in a substrate; a plurality of capacitor plugs on the plurality of drain regions; a plurality of lower electrodes on the plurality of capacitor plugs and respectively including a U-shaped cross-sectional profile; a lower supporting layer above the substrate, against on outer surfaces of the plurality of lower electrodes, and including: a plurality of first openings along the lower supporting layer and between the plurality of lower electrodes; and a higher supporting layer above the lower supporting layer, against on the outer surfaces of the plurality of lower electrodes, and including: a plurality of second openings along the higher supporting layer and topographically aligned with the plurality of first openings. The widths of the plurality of first openings and the widths of the plurality of second openings are substantially the same.

Abstract: The present application provides a memory device and a method of manufacturing the memory device.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors topographically aligned with the first die include a first density. The plurality of middle interconnectors topographically aligned with the second die include a second density different from the first density.

Abstract: The present application provides a memory device and a method of manufacturing the memory device.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a drain region positioned in the substrate; a common source region positioned in the substrate and opposing to the drain region; a bit line structure including a bit line conductive layer positioned on the substrate and electrically coupled to the common source region; a cell contact positioned on the substrate, adjacent to the bit line structure, and electrically connected to the drain region; a landing pad positioned above the bit line conductive layer and electrically connected to the cell contact; and an air gap positioned between the landing pad and the bit line conductive layer.

Abstract: A method for preparing a semiconductor device, includes: forming a first dielectric structure and a second dielectric structure over a semiconductor substrate; forming a conductive material over the first dielectric structure and the second dielectric structure, wherein the conductive material extends into a first opening between the first dielectric structure and the second dielectric structure; partially removing the conductive material to form a first bit line and a second bit line in the first opening; forming a first capacitor contact and a second capacitor contact in the first dielectric structure and the second dielectric structure, respectively; forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate; and forming a first capacitor and a second capacitor over the first capacitor contact and the second capacitor contact, respectively.

Abstract: A semiconductor device structure includes a first hard mask pattern disposed over a metal layer. The semiconductor device structure also includes a second hard mask pattern disposed over the metal layer and spaced apart from the first hard mask pattern. A bottom surface of the first hard mask pattern is coplanar with a bottom surface of the second hard mask pattern.

Abstract: A semiconductor device structure includes a first hard mask pattern disposed over a metal layer. The semiconductor device structure also includes a second hard mask pattern disposed over the metal layer and spaced apart from the first hard mask pattern. A bottom surface of the first hard mask pattern is coplanar with a bottom surface of the second hard mask pattern.

Abstract: A semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a plurality of drain regions in a substrate; a plurality of capacitor plugs on the plurality of drain regions; a plurality of lower electrodes on the plurality of capacitor plugs and respectively including a U-shaped cross-sectional profile; a lower supporting layer above the substrate, against on outer surfaces of the plurality of lower electrodes, and including: a plurality of first openings along the lower supporting layer and between the plurality of lower electrodes; and a higher supporting layer above the lower supporting layer, against on the outer surfaces of the plurality of lower electrodes, and including a plurality of second openings along the higher supporting layer and topographically aligned with the plurality of first openings. The widths of the first openings and the widths of the second openings are substantially the same.

Abstract: A semiconductor device includes a plurality of drain regions in a substrate; a plurality of capacitor plugs on the plurality of drain regions; a plurality of lower electrodes on the plurality of capacitor plugs and respectively including a U-shaped cross-sectional profile; a lower supporting layer above the substrate, against on outer surfaces of the plurality of lower electrodes, and including: a plurality of first openings along the lower supporting layer and between the plurality of lower electrodes; and a higher supporting layer above the lower supporting layer, against on the outer surfaces of the plurality of lower electrodes, and including: a plurality of second openings along the higher supporting layer and topographically aligned with the plurality of first openings. The widths of the plurality of first openings and the widths of the plurality of second openings are substantially the same.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.

Abstract: A method for preparing a semiconductor device, includes: forming a first dielectric structure and a second dielectric structure over a semiconductor substrate; forming a conductive material over the first dielectric structure and the second dielectric structure, wherein the conductive material extends into a first opening between the first dielectric structure and the second dielectric structure; partially removing the conductive material to form a first bit line and a second bit line in the first opening; forming a first capacitor contact and a second capacitor contact in the first dielectric structure and the second dielectric structure, respectively; forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate; and forming a first capacitor and a second capacitor over the first capacitor contact and the second capacitor contact, respectively.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first stack structure positioned on a first substrate, a first impurity region and a second impurity region respectively positioned on opposing sides of the first stack structure and operatively associated with the first stack structure, a second stack structure positioned above the first stack structure with a middle insulation layer interposed therebetween, and a third impurity region positioned on one side of the second stack structure and electrically coupled to the second impurity region. The first stack structure includes a plurality of first semiconductor layers and a plurality of gate assemblies alternatively arranged. The plurality of gate assemblies includes a gate dielectric and a gate electrode. The second stack structure includes a plurality of second semiconductor layers and a plurality of capacitor sub-units alternatively arranged.

Abstract: A method for preparing a semiconductor device, includes: forming a first dielectric structure and a second dielectric structure over a semiconductor substrate; forming a conductive material over the first dielectric structure and the second dielectric structure, wherein the conductive material extends into a first opening between the first dielectric structure and the second dielectric structure; partially removing the conductive material to form a first bit line and a second bit line in the first opening; forming a first capacitor contact and a second capacitor contact in the first dielectric structure and the second dielectric structure, respectively; forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate; and forming a first capacitor and a second capacitor over the first capacitor contact and the second capacitor contact, respectively.

Abstract: The present application provides a memory device and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with an active area over or in the semiconductor substrate and including a recess surrounding the active area; a first dielectric layer disposed over the active area of the semiconductor substrate; a second dielectric layer disposed over the first dielectric layer; and an isolation member disposed within the recess and entirely surrounding the active area.

Abstract: The present application provides a memory device and a method of manufacturing the memory device.