Patents by Inventor Liang-Po Chen

Liang-Po Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170276292
    Abstract: The tilt prevention structure for a test seat contains a track element having at least a notch configured on a top side of the track element, a base member having a trough on a bottom side for detachably accommodating the track element and at least a fastening hole on a front side connecting the trough, and at least a limiting element plugged into the fastening hole. The track element is fixedly configured on a test apparatus. The base member is then joined to the track element by embedding the track element in the trough. The limiting elements are plugged into the fastening holes so as to prevent the base member from tilting. The base member can be moved along the track element so as to align the adjustment member against an object to be tested.
    Type: Application
    Filed: March 22, 2016
    Publication date: September 28, 2017
    Inventors: YU-CHUAN CHU, LIANG-PO CHEN
  • Publication number: 20170276703
    Abstract: The structure of a laser cleaning machine contains a laser generation device for cleaning a to-be-cleaned object, a platform for supporting the to-be-cleaned object under a projection path of the laser generation device, an image capture device configured on the laser generation device, and a cleaning and control device inside the image capturing device for setting a traversal path of the laser generation device and for processing information obtained by the image capturing device. The image capturing device contains a first capturing element and a second capturing element to a side of the first capturing element. The cleaning and control device obtains the location distribution and the precise coordinate of each contactor element on the to-be-cleaned object, and then determines an optimized traversal path and instructs the laser generation device to conduct cleaning accordingly so as to achieves high-quality and highly efficient cleaning.
    Type: Application
    Filed: March 22, 2016
    Publication date: September 28, 2017
    Inventors: LIANG-PO CHEN, SHANG-WEI CHIANG
  • Publication number: 20130338959
    Abstract: A switching-type categorizing and testing apparatus of a Radio Frequency integrated Circuit (RFIC) is used to test and categorize at least one RFIC module. The apparatus comprises at least one testing module and a plurality of categorizing modules. The testing module is used to test the RFIC module, and the categorizing modules comprise a first categorizing module and a second categorizing module. The testing module tests the RFIC module within one of the two categorizing modules at the same when the other categorizing module categorizes the RFIC module already tested. The present invention may further increase the testing and categorizing quantity so as to achieve the fast and cost-saving advantages.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Inventors: YUN-PENG HO, Liang-Po Chen
  • Patent number: 5913123
    Abstract: A method for manufacturing a deep-submicron P-type metal-oxide semiconductor shallow junction utilizes an electron terminal structure with a base covered by a layer containing boron, germanium, and silicon. This layer containing boron, germanium, and silicon ("B--Ge--Si") is used as a shield during ion implanting and as an impurity ion source to form a high diffusion ion concentration at a shallow junction of the semiconductor base or substrate. The B--Ge--Si layer can be thoroughly removed using selective corrosive erosion. Due to the simplicity of this invention's manufacturing process, it can be used for deep-submicron PMOS component production, and thus, it has great practical value.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: June 15, 1999
    Assignee: National Science Council
    Inventors: Horng-Chih Lin, Jien-Sheng Chao, Liang-Po Chen
  • Patent number: 5658806
    Abstract: A method for fabricating a self-aligned thin-film transistor, in accordance with the present invention, first involves forming a gate electrode on an insulating layer. Next, a gate dielectric layer is formed to enclose the gate electrode. Subsequently, a semiconductor layer, a conducting layer, and a first dielectric layer are formed to cover the substrate and the gate dielectric layer. Afterwards, a chemical mechanical polishing process is applied to subsequently polish the first dielectric layer and the conducting layer to expose the semiconductor layer above the gate electrode. Therefore, the conducting layer disposed at opposite sides of the gate electrode is self-aligned to act as the source/drain regions of the fabricated TFT device.
    Type: Grant
    Filed: October 26, 1995
    Date of Patent: August 19, 1997
    Assignee: National Science Council
    Inventors: Horng-Chih Lin, Liang-Po Chen, Hsiao-Yi Lin, Chun-Yen Chang