Abstract: A sweeping assembly for a cleaning device, includes: a brush holder defining an accommodating cavity therein; a main brushroll accommodated in the accommodating cavity of the brush holder, the main brushroll including a cleaning part located at a middle portion of the main brushroll and a connecting part located at an end of the main brushroll, the connecting part being connected to the brush holder or a driver of the cleaning device; and an anti-winding structure arranged at the brush holder, and including a first end connected to the brush holder, and a second end abutting against the brushroll.

Abstract: This application discloses a directional measurement method and a device. In this one example solution, a terminal device may determine a to-be-measured receive beam, and perform received signal strength indication (RSSI) measurement on the to-be-measured receive beam. The terminal device may perform RSSI measurement on the to-be-measured receive beam in a targeted manner, and does not need to perform RSSI measurement in all directions. Therefore, directional RSSI measurement of the terminal device can be implemented.

Abstract: A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit coupled between the current control circuit and a ground. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. First terminals of the first transistors each is in connection with one of the bit lines. Second terminals of the first transistors each is in connection with the discharge enable circuit. Third terminals of the first transistors are in connection with a reference current generator of the current control circuit.

Abstract: The disclosure provides a composition comprising (a) one or more isolated bacterial metabolites selected from prednicarbate, N-palmitoyl-D-threonine and 3,3-difluoro-5-alpha-androstan-17-beta-yl-acetate, and (b) a pharmaceutically acceptable carrier, and use of such composition for reducing inflammation and/or treating an inflammatory disorder in a subject in need thereof.

Abstract: The present disclosure relates to a soft magnetic composite with a two-dimensional magnetic moment and a high working frequency band, and a preparation method therefor. According to an embodiment, the soft magnetic composite with a two-dimensional magnetic moment may comprise: an insulating matrix; and two-dimensional magnetic moment micropowder dispersed in the insulating matrix, wherein inside the two-dimensional magnetic moment micropowder, a magnetic moment is distributed in a specific two-dimensional plane. The soft magnetic composite with a two-dimensional magnetic moment of the present disclosure has a higher cut-off frequency than existing materials, and therefore can be widely applied in the field of high frequency microwave application.

Abstract: The present application discloses a memory device, a programming method and a memory system. The memory device comprises: a memory cell array comprising a plurality of word lines and a plurality of bit lines; each of the word lines comprising at least two word line segments; each of the word line segment in the word line having different signal transmission distances from a word line driver; different word line segments in the word line corresponding to different bit lines respectively; the word line driver configured to apply a word line voltage to the word line; a bit line driver configured to apply different bias voltages to different bit lines corresponding to the different word line segments respectively during application of a programming pulse.

Abstract: The present disclosure provides a method for controlling bit line voltages in a three-dimensional memory device. The method includes ramping up a bit line clamp regulation voltage and a control signal regulation voltage. The method also includes ramping up a bit line clamp enabling voltage and a control signal enabling voltage. The method also includes increasing a bit line clamp voltage in one stage, and increasing a control signal voltage in two stages. The method also includes decreasing the control signal voltage. The method also includes ramping down the bit line clamp enabling voltage, the bit line clamp regulation voltage, the control signal enabling voltage, and the control signal regulation voltage. The method further includes decreasing the bit line clamp voltage.

Abstract: A method of operating a memory device is disclosed. The memory device includes a memory string coupled with a bit line and a common source line. An erase voltage is applied to the bit line and the common source line in an erase operation. The bit line and the common source line are discharged in a discharge operation after the erase operation. A voltage difference between the bit line and the common source line is less than a first predetermined value during a period of the discharge operation.

Abstract: A cleaning device is disclosed that includes a main body, a cleaning assembly, and a connection mechanism. The cleaning device further includes a cleaning liquid supply system including a cleaning liquid reservoir and a cleaning liquid output pipeline; and a dirt recovery system including a dirt reservoir, a dirt suction pipeline and a fan assembly. The connection mechanism is configured to connect the main body and the cleaning assembly, and includes at least two rotational connection portions, rotation axes of which are not parallel to each other; and the at least two rotational connection portions are configured to enable the main body to rotate relative to the cleaning assembly about the rotation axis of each of the at least two rotational connection portions.

Abstract: The present disclosure provides a method for controlling a 3D NAND memory using a read operation. The method can include increasing a voltage to a plurality of top select gates, with respect to a first reference voltage level, during a pre-pulse period of the read operation prior to a read period of the read operation. The method can also include increasing a voltage to a plurality of word lines, with respect to a second reference voltage level, during the pre-pulse period. The method can also include decreasing a voltage to a bit line, with respect to the first voltage, during the pre-pulse period. The method can also include applying no voltage change to a bottom select gate during the pre-pulse period.

Abstract: Devices, systems, and methods for counting a quantity of fail-bits in a memory device using a VFC circuit are disclosed. The VFC circuit can be calibrated via an offset adjustment mechanism to compensate an internal mismatch. The VFC circuit can include a processing unit and a circuit coupled to the processing unit. The processing unit can receive a first signal representing a number of detected fail-bits in the memory array, process the first signal and an offset signal, and generate a second signal representing a quantity of fail-bits. The circuit can receive the first and second signals, determine a difference between the quantity of fail-bits represented by the second signal and the number of detected fail-bits represented by the first signal, adjust the offset signal according to the difference, and provide the offset signal to the processing unit.

Abstract: The present disclosure provides a method for discharging a memory device after an erase operation. The method comprises grounding a source line of the memory device; and switching on a discharge transistor to connect a bit line of the memory device to the source line by maintaining a constant voltage difference between a gate terminal of the discharge transistor and the source line. The method also includes comparing an electrical potential of the source line with a first predetermined value; and floating the gate terminal of the discharge transistor when the electrical potential of the source line is lower than the first predetermined value.

Abstract: Aspects of the present disclosure provide a memory, a control method thereof, and a memory system. The memory includes a memory cell array and a peripheral circuit, the peripheral circuit comprising at least a trigger circuit comprising a reference signal output circuit and a fail bit signal output circuit, wherein the fail bit signal output circuit is configured to generate a fail bit signal according to a test signal obtained from verification of the memory, and the reference signal output circuit is configured to output a plurality of reference signals; and a comparator coupled with the trigger circuit and configured to compare the fail bit signal with the at least one reference signal to output a verification result.

Abstract: In this application, a synchronization raster design method and an apparatus are provided. The method includes: A network device determines a first bandwidth. A frequency range corresponding to the first bandwidth is above 52.6 gigahertz GHz. The network device configures a plurality of synchronization rasters in the first bandwidth according to a first rule. One synchronization signal block SSB is placed on each synchronization raster, and each synchronization raster corresponds to one global synchronization number. According to the synchronization raster design method provided in this application, an adaptive first bandwidth can be provided for different subcarrier spacings. This reduces power consumption of the terminal device and improves SSB search efficiency of the terminal device.

Abstract: A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit coupled between the current control circuit and a ground. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. First terminals of the first transistors each is in connection with one of the bit lines. Second terminals of the first transistors each is in connection with the discharge enable circuit. Third terminals of the first transistors are in connection with a reference current generator of the current control circuit.

Abstract: A method, device, and apparatus for synthesizing a motion sequence of a virtual object and a non-transitory computer-readable storage medium are disclosed. The method can include obtaining description information of a motion sequence of a virtual object, and determining a continuous motion clip set similar to at least some motions in the motion sequence based on the description information and a continuous motion clip library constructed with video materials. The method can further include synthesizing the motion sequence of the virtual object based on the continuous motion clip set, where each continuous motion clip in the continuous motion clip library includes a unique identifier of the continuous motion clip, motion information of the continuous motion clip, and a representation vector corresponding to the each continuous motion clip.

Abstract: A sweeping assembly for a cleaning device, includes: a brush holder defining an accommodating cavity therein; a main brushroll accommodated in the accommodating cavity of the brush holder, the main brushroll including a cleaning part located at a middle portion of the main brushroll and a connecting part located at an end of the main brushroll, the connecting part being connected to the brush holder or a driver of the cleaning device; and an anti-winding structure arranged at the brush holder, and including a first end connected to the brush holder, and a second end abutting against the brushroll.

Abstract: The present disclosure provides a method for controlling a 3D NAND memory using a read operation. The method can include increasing a voltage to a plurality of top select gates, with respect to a first reference voltage level, during a pre-pulse period of the read operation prior to a read period of the read operation. The method can also include increasing a voltage to a plurality of word lines, with respect to a second reference voltage level, during the pre-pulse period. The method can also include decreasing a voltage to a bit line, with respect to the first voltage, during the pre-pulse period. The method can also include applying no voltage change to a bottom select gate during the pre-pulse period.

Abstract: Methods and an apparatuses for recognizing a text, recognition devices and storage media are provided, which belong to the field of text detections. A method includes: extracting, by the recognition device, a feature map of a to-be-recognized image, then determining segmentation information of a text region of the to-be-recognized image based on a preset segmentation network and the feature map, and then determining boundary key points in the text region based on the segmentation information, and then converting a text in the text region into a text with a target arrangement sequence based on the boundary key points and then inputting the text obtained by conversion into a preset recognition model for recognition processing.

Abstract: A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. The current control circuit is coupled to the plurality of bit lines to control a discharge current in a discharge operation. The discharge enable circuit is coupled to the current control circuit to enable the discharge operation. The discharge operation discharges a charge on the plurality of bit lines.