Abstract: The present disclosure describes a semiconductor structure that can provide improved gap fill. The semiconductor structure can include conductive features disposed on a first layer separated by a distance and a layer disposed over the conductive features and the first layer. The layer can include triangular-shaped peaks above each conductive feature in the conductive features and valley regions above the first layer.

Abstract: A metal-insulator-metal (MIM) device includes a first metal, a first cap layer disposed on the first metal, an insulator layer disposed on the first cap layer, a second cap layer disposed on the insulator layer, and a second metal disposed on the second cap layer. The first and second cap layers each comprise a dielectric material having a tetragonal crystal phase. In some embodiments, the tetragonal phase percentage of the cap layers is at least 80%. In some embodiments, the insulator layer is a ferroelectric material, such as Hf1-xZrxO2 with an orthorhombic phase percentage of at least 70%. In some such embodiments, the cap layers are ZrO2 or Hf1-xZrxO2 with a higher Zr fraction than the insulator layer. In some embodiments, the cap layers are doped with a dopant that causes the tetragonal phase percentage of the cap layers to be at least 80%.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device having a mark. The method includes: providing a substrate including a device region and a peripheral region adjacent to the device region; forming an interconnect layer over the substrate; depositing a first dielectric layer on the interconnect layer; forming a redistribution layer (RDL) over the first dielectric layer in the device region; depositing a second dielectric layer on the RDL in the device region and the first dielectric layer in the device region and the peripheral region; and removing portions of the second dielectric layer, the first dielectric layer and the interconnect structure in the peripheral region to form the mark in the peripheral region.

Abstract: A method for manufacturing a semiconductor structure is provided. A first plate, a second plate, and a third plate are sequentially formed over a substrate. The first plate includes a first top surface, first sidewalls and first transition regions, wherein the first transition regions connect the first sidewalls to the first top surface. The second plate includes a second top surface, second sidewalls and second transition regions, wherein the second transition regions connect the second sidewalls to the second top surface, and the first transition regions are covered by the second plate. The third plate includes a third top surface, third sidewalls and third transition regions, wherein the third transition regions connect the third sidewalls to the third top surface, and the second transition regions are exposed by the third plate. A semiconductor structure thereof is also provided.

Abstract: Some embodiments relate to an integrated chip including a first metal insulator metal (MIM) capacitor disposed over a substrate. The integrated chip further includes a second MIM capacitor disposed over the substrate. The first MIM capacitor has a first outer sidewall facing a second outer sidewall of the second MIM capacitor. A dielectric structure is arranged over and laterally between the first MIM capacitor and the second MIM capacitor. A base conductive layer is arranged between the first MIM capacitor and the second MIM capacitor and has a substantially flat upper surface. A metal core arranged on the substantially flat upper surface of the base conductive layer.

Abstract: A semiconductor assembly includes a semiconductor device and a seal ring. The seal ring is disposed adjacent to the semiconductor device. The seal ring includes a first side surface inclined from a top surface of the seal ring toward a bottom surface of the seal ring, wherein a lateral width of the bottom surface of the seal ring is larger than a lateral width of the top surface of the seal ring; and a first metal line disposed in the seal ring and comprising a second side surface adjacent to the first side surface of the seal ring. A maximum distance between the second side surface of the first metal line and the first side surface of the seal ring is in a range of 5 ?m to 30 ?m.

Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing a semiconductor structure. The semiconductor structure includes a first set of photoresist structures, a second photoresist structure, and a third photoresist structure. The first set of photoresist structures is disposed along a first orientation. The second photoresist structure is disposed non-parallel to the first orientation. The third photoresist structure is disposed non-parallel to the first orientation. The second photoresist structure and the third photoresist structure contact at least one of the first set of photoresist structures.