Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a gate electrode disposed on a substrate. Source/drain regions are disposed on or within the substrate along opposing sides of the gate electrode. A noise reducing component is arranged along an upper surface of the gate electrode and/or along an upper surface of the substrate over the source/drain regions. A cap layer covers the upper surface of the gate electrode and/or the upper surface of the substrate over the source/drain regions. An inter-level dielectric (ILD) is disposed over and along one or more sidewalls of the cap layer.

Abstract: A semiconductor structure includes a semiconductor substrate, a serpentine-shaped resistor, and a MOS transistor. The semiconductor substrate includes an isolation structure and an active region. The serpentine-shaped resistor is over the isolation structure. The serpentine-shaped resistor extends in a length direction and has a width that is equal to or greater than about 3.6 ?m in a width direction. The MOS transistor is over the active region of the semiconductor substrate.

Abstract: Voltage reference circuits are provided. A voltage reference circuit includes a first transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit, and an output note. The first transistor is formed by a plurality of second transistors. A gate and a drain of the flipped-gate transistor are coupled to a gate and a drain of each second transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and a mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the first transistor in response to the mirroring current. The output node is coupled to a source of each second transistor and the second current mirror unit, and configured to output a reference voltage. Size of the flipped-gate transistor is less than that of the first transistor.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

Abstract: Voltage reference circuits are provided. A voltage reference circuit includes a transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit and an output node. The gate and the drain of the flipped-gate transistor are coupled to the gate and the drain of the transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and the mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the transistor in response to the mirroring current. The output node is coupled to the source of the transistor and the second current mirror unit, and is configured to output a reference voltage.

Abstract: Voltage reference circuits are provided. A voltage reference circuit includes a transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit and an output node. The gate and the drain of the flipped-gate transistor are coupled to the gate and the drain of the transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and the mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the transistor in response to the mirroring current. The output node is coupled to the source of the transistor and the second current mirror unit, and is configured to output a reference voltage.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

Abstract: A memory cell includes a first transistor coupled to a source line, wherein the first transistor is in a first well. The memory cell further includes a second transistor coupled to the first transistor and a bit line, wherein the second transistor is in the first well. The memory cell further includes a first capacitor coupled to a word line and the second transistor, wherein the first capacitor is in a second well. The memory cell further includes a second capacitor coupled to the second transistor and an erase gate, wherein the second capacitor is in the second well. In some embodiments, the first well contacts the second well on a first side of the first well.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

Abstract: A memory cell includes a first transistor coupled to a source line, wherein the first transistor is in a first well. The memory cell further includes a second transistor coupled to the first transistor and a bit line, wherein the second transistor is in the first well. The memory cell further includes a first capacitor coupled to a word line and the second transistor, wherein the first capacitor is in a second well. The memory cell further includes a second capacitor coupled to the second transistor and an erase gate, wherein the second capacitor is in the second well. In some embodiments, the first well contacts the second well on a first side of the first well.

Abstract: A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.

Abstract: A non-volatile memory structure includes a semiconductor substrate and a first layer of a first dopant type in the semiconductor substrate. The non-volatile memory structure further includes a first well region of a second dopant type over the first layer, a second well region of the second dopant type over the first layer and spaced apart from the first well region, and a third well region of the first dopant type disposed between the first well region and the second well region and extending downward to the first layer.

Abstract: A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.

Abstract: A non-volatile memory structure includes a semiconductor substrate and a first layer of a first dopant type in the semiconductor substrate. The non-volatile memory structure further includes a first well region of a second dopant type over the first layer, a second well region of the second dopant type over the first layer and spaced apart from the first well region, and a third well region of the first dopant type disposed between the first well region and the second well region and extending downward to the first layer.

Abstract: A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.

Abstract: Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage. The capacitor has a first plate and a second plate, and the first plate of the capacitor is electrically connected to a gate of the first transistor. The second plate of the capacitor is connected to a corresponding word line. The switch is turned off when the memory cell is not selected to perform a write operation or a read operation.

Abstract: A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.