Abstract: An on chip test system for arrays is provided that includes self test and maintenance operation while allowing for both synchronous and pipeline modes of normal operation. The system is integrated on a chip that includes a plurality of inputs and a plurality of outputs. A plurality of gates are coupled between the plurality of inputs and outputs wherein input signals may be transmitted asynchronously to the gates and output signals may be transmitted asynchronously to the outputs. An input shift register is coupled between each of the inputs and the gates for synchronously transmitting input signals, and an output shift register is coupled between the gates and each of the outputs for synchronously transmitting output signals. A control logic circuit is coupled to the plurality of gates, the input shift registers, and the output shift registers for selecting the systems mode of operation. A comparator circuit is coupled to the output shift registers for comparing said output signals with expected signals.

Abstract: An on-chip memory control circuit generates a proper WRITE STROBE signal for a clock synchronized pipe-line operated integrated circuit memory. A symmetrical clock signal having half the frequency of the system clock is produced by applying the system clock to the C input of a standard master slave delay type flip-flop having its Q output fed back to its D input. A negative going pulse train .phi..sub.P comprising a pulse at every transition of the symmetrical clock is generated by a level change detector which issues a pulse of a desired width whenever a level change at its input is detected. A delayed pulse train .phi..sub.PD is produced by delaying .phi..sub.P an amount which depends on the speed of the memory and other design criteria. The pulse drains .phi..sub.P and .phi..sub.PD are applied to an asynchronous flip-flop, the output of which corresponds to the desired WRITE STROBE signal.