Patents by Inventor Liang-Wei Chiu

Liang-Wei Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11552052
    Abstract: A semiconductor device includes a first metal-oxide semiconductor (MOS) transistor on a first substrate, a first interlayer dielectric (ILD) layer on the first MOS transistor, a second substrate on the first ILD layer, and a second MOS transistor on a second substrate. Preferably, the semiconductor device includes a static random access memory (SRAM) and the SRAM includes a first pull-up device, a second pull-up device, a first pull-down device, a second pull-down device, a first pass-gate device, a second pass-gate device, a read port pull-down device, and a read port pass-gate device, in which the read port pull-down device includes the first MOS transistor and the read port pass-gate device includes the second MOS transistor.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: January 10, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Yu Shen, Tsung-Hsun Wu, Liang-Wei Chiu, Shih-Hao Liang
  • Patent number: 11322215
    Abstract: A one-time programmable (OTP) memory device includes a first memory cell, which further includes a first source line extending along a first direction on a substrate, a first word line extending along the first direction on one side of the first source line, a second word line extending along the first direction on another side of the first source line, a first diffusion region extending along a second direction adjacent to two sides of the first word line and the second word line, and a first metal interconnection connecting the first word line and the second word line.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: May 3, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pin Tsao, Tsung-Hsun Wu, Liang-Wei Chiu, Kuo-Hsing Lee, Sheng-Yuan Hsueh, Kun-Hsien Lee, Chang-Chien Wong
  • Publication number: 20210296286
    Abstract: A semiconductor device includes a first metal-oxide semiconductor (MOS) transistor on a first substrate, a first interlayer dielectric (ILD) layer on the first MOS transistor, a second substrate on the first ILD layer, and a second MOS transistor on a second substrate. Preferably, the semiconductor device includes a static random access memory (SRAM) and the SRAM includes a first pull-up device, a second pull-up device, a first pull-down device, a second pull-down device, a first pass-gate device, a second pass-gate device, a read port pull-down device, and a read port pass-gate device, in which the read port pull-down device includes the first MOS transistor and the read port pass-gate device includes the second MOS transistor.
    Type: Application
    Filed: April 15, 2020
    Publication date: September 23, 2021
    Inventors: Yen-Yu Shen, Tsung-Hsun Wu, Liang-Wei Chiu, Shih-Hao Liang