Abstract: The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.

Abstract: The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.

Abstract: A newly identified protein that is encoded by a polynucleotide sequence associated with cytoplasmic male sterility restorer activity (Rf3) is described. The cytoplasmic male sterility restorer gene can be inserted through breeding introgression into plant genomes to restore cytoplasmic male sterility in plants. Further applications of the newly identified polynucleotide sequence associated with cytoplasmic male sterility restorer activity include a mutation (rf3) which results in cytoplasmic male sterility. The cytoplasmic male sterility restorer gene can be inserted through breeding introgression into plant genomes to result in cytoplasmic male sterility in plants. Methods for detecting the cytoplasmic male sterility restorer (Rf3) and the cytoplasmic male sterility (rf3) gene sequences are further described.

Abstract: A method for forming a semiconductor device includes steps as follows: Firstly, a semiconductor substrate having a circuit element with at least one spacer formed thereon is provided. Next, an acid treatment is performed on a surface of the spacer. A disposable layer is then formed on the circuit element and the spacer. Thereafter, an etching process is performed to form at least one recess in the semiconductor substrate adjacent to the circuit element. Subsequently, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in the recess.

Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.

Abstract: The invention provides a fabricating method of a FinFET, comprising: providing a substrate having fin structures; depositing an dielectric layer on the substrate filling between the fin structures; forming recesses to reveal a portion of the fin structure by removing a portion of the dielectric layer; performing a cleaning process on using a cleaning solution selected from one of a first solution, consisting of dHF and H2O2, and a second solution, consisting of dHF and DIO3; forming a gate structure across on the fin structures; and forming a source/drain structure on the substrate at two lateral sides of the gate structure. The present invention also provides a fabricating method of a FinFET having an improved cleaning step using a cleaning solution having one of a third solution, consisting of dHF and DIO3, and a fourth solution, consisting of NH4OH and DIO3 before formation of the source/drain structure.

Abstract: A method for fabricating a semiconductor structure includes following steps. First, a first layer, a second layer and a third layer are sequentially formed on the substrate. The second layer is conformally disposed on the top surface of the first layer. The second layer and the first layer have different compositions, and the third layer and the second layer also have different compositions. Then, a planarizing process is performed on the third layer until portions of the second layer are exposed. Afterwards, hydrofluoric acid and aqueous oxidant are concurrently or sequentially provided to the remaining second and third layers. Finally, an etch back process is carried out to remove all the second layer and portions of the first layer.

Abstract: A method for fabricating a semiconductor structure includes following steps. First, a first layer, a second layer and a third layer are sequentially formed on the substrate. The second layer is conformally disposed on the top surface of the first layer. The second layer and the first layer have different compositions, and the third layer and the second layer also have different compositions. Then, a planarizing process is performed on the third layer until portions of the second layer are exposed. Afterwards, hydrofluoric acid and aqueous oxidant are concurrently or sequentially provided to the remaining second and third layers. Finally, an etch back process is carried out to remove all the second layer and portions of the first layer.

Abstract: A method for forming a semiconductor device includes steps as follows: Firstly, a semiconductor substrate having a circuit element with at least one spacer formed thereon is provided. Next, an acid treatment is performed on a surface of the spacer. A disposable layer is then formed on the circuit element and the spacer. Thereafter, an etching process is performed to form at least one recess in the semiconductor substrate adjacent to the circuit element. Subsequently, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in the recess.

Abstract: A method for fabricating the semiconductor device is disclosed. A semiconductor substrate having a main surface is provided. A gate is formed on the main surface of the semiconductor substrate. An offset liner is formed on the sidewall of the gate. An ion implantation process is performed to form lightly doped drain (LDD) region in the semiconductor substrate. A spacer is formed on a sidewall of the gate. A cavity is recessed into the main surface of the semiconductor substrate. The cavity is adjacent to the spacer. An epitaxial layer is grown in the cavity. The spacer is then subjected to a surface treatment to form a dense oxide film on the spacer. A mask layer is deposited on the dense oxide film. The dense oxide film has a thickness that is smaller or equal to 12 angstroms.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, an ILD layer on the semiconductor substrate, a gate in the ILD layer, an offset liner on a sidewall of the gate, a spacer on the offset liner, a dense oxide film on the spacer, a contact etch stop layer on the dense oxide film, and a contact plug adjacent to the contact etch stop layer. The semiconductor device further includes a source region in the semiconductor substrate and a drain region spaced apart from the source region. A channel is located between the source region and the drain region.

Abstract: A method of forming a multilayer hard mask includes the following steps. An unpatterned multilayer hard mask is formed on a semiconductor substrate. The unpatterned multilayer hard mask includes a first hard mask layer formed on the semiconductor substrate and a second hard mask layer directly formed on the first hard mask layer. A treatment is performed on a top surface of the first hard mask layer before the step of forming the second hard mask layer, and the treatment is configured to remove impurities on the first hard mask layer and form dangling bonds on the top surface of the first hard mask layer. Defects related to the first hard mask layer and the second hard mask layer may be reduced, and the manufacturing yield may be enhanced accordingly.

Abstract: A method of an interfacial oxide layer formation comprises a plurality of steps. The step (S1) is to remove a native oxide layer from a surface of a substrate; the step (S2) is to form an oxide layer on a surface of a substrate by piranha solution (SPM); the step (S3) is to cleaning a surface of the oxide layer by standard clean 1 (SC1), and the step (S4) is to etch he oxide layer by a solution comprising diluted hydrogen fluoride (dHF) and ozonized pure water (DIO3).

Abstract: An example information query method including receiving a query parameter including keyword information and one or more pieces of language feature information; generating one or more query request strings corresponding to the one or more pieces of language feature information respectively according to the keyword information; determining corresponding position intervals of the one or more pieces of language feature information in a second index according to a pre-established first index, the first index including a mapping relationship between the language feature information and the position intervals of the second index, the second index including a mapping relationship between keywords and information pages; and acquiring query results corresponding to the one or more query request strings respectively according to the determined corresponding position intervals of the one or more pieces of language feature information in the second index.

Abstract: A method of an interfacial oxide layer formation comprises a plurality of steps. The step (S1) is to remove a native oxide layer from a surface of a substrate; the step (S2) is to form an oxide layer on a surface of a substrate by piranha solution (SPM); the step (S3) is to cleaning a surface of the oxide layer by standard clean 1 (SC1), and the step (S4) is to etch he oxide layer by a solution comprising diluted hydrogen fluoride (dHF) and ozonized pure water (DIO3).

Abstract: A newly identified protein that is encoded by a polynucleotide sequence associated with cytoplasmic male sterility restorer activity (Rf3) is described. The cytoplasmic male sterility restorer gene can be inserted through breeding introgression into plant genomes to restore cytoplasmic male sterility in plants. Further applications of the newly identified polynucleotide sequence associated with cytoplasmic male sterility restorer activity include a mutation (rf3) which results in cytoplasmic male sterility. The cytoplasmic male sterility restorer gene can be inserted through breeding introgression into plant genomes to result in cytoplasmic male sterility in plants. Methods for detecting the cytoplasmic male sterility restorer (Rf3) and the cytoplasmic male sterility (rf3) gene sequences are further described.

Abstract: A high-voltage surge protective connector for connecting with an external cable is disclosed. The connector includes a first connecting end, a second connecting end, a transformer, and a protection module. The second connecting end is connected with the external cable. The transformer includes a primary coil and a secondary coil. The primary coil is electrically connected with the first connecting end, and the secondary coil is electrically connected with the second connecting end. The secondary coil includes a center tap. The protection module is disposed between the center tap and the ground. The protection module includes a first portion and a second portion. The first portion is electrically connected with the ground. A gap exists between the first portion and the second portion. A point discharge happens between the first portion and the second portion when the high-voltage surge is generated.

Abstract: A low-resistivity, doped zinc oxide coated glass article is formed by providing a hot glass substrate having a surface on which a coating is to be deposited, the surface being at a temperature of at least 400° C. A zinc containing compound, an oxygen-containing compound and an aluminum- or gallium-containing compound are directed to the surface on which the coating is to be deposited. The zinc containing compound, oxygen-containing compound, and aluminum- or gallium-containing compound are mixed together for a sufficient time that an aluminum or gallium doped zinc oxide coating is formed on the surface at a deposition rate of greater than 5 nm/second.

Abstract: What is described and claimed is an atmospheric chemical vapor deposition method of making a low-resistivity, doped zinc oxide coated glass article, made by directing one or more streams of gaseous reactants, specifically a zinc containing compound, a fluorine containing compound, an oxygen containing compound, and at least one compound containing one or more of boron, aluminum, gallium and indium onto a surface of a heated glass substrate.