Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.

Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.

Abstract: A liquid crystal panel includes a substrate and a display medium layer. The display medium layer is located on the substrate. The display medium layer includes multiple first liquid crystal capsules and multiple second liquid crystal capsules. Each of the first liquid crystal capsules includes multiple first liquid crystal molecules. A dielectric anisotropy ?? of the first liquid crystal molecules is greater than 0. A refractive index of the first liquid crystal capsules on the z-axis is greater than refractive indices of the first liquid crystal capsules on the x-axis and on the y-axis. Each of the second liquid crystal capsules includes second liquid crystal molecules. A dielectric anisotropy ?? of the second liquid crystal molecules is greater than 0. A refractive index of the second liquid crystal capsules on the z-axis is smaller than refractive indices of the second liquid crystal capsules on the x-axis and on the y-axis.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

Abstract: A finFET device and methods of forming a finFET device are provided. The device includes a fin and a capping layer over the fin. The device also includes a gate stack over the fin, the gate stack including a gate electrode and a gate dielectric. The gate dielectric extends along sidewalls of the capping layer. The device further includes a gate spacer adjacent to sidewalls of the gate electrode, the capping layer being interposed between the gate spacer and the fin.

Abstract: The present invention relates to a use of Discoidin Domain Receptor 1 (DDR1) inhibitor in preparing a medicament for preventing or treating a joint disease. The present invention further relates to a use of DDR1 activator in preparing a medicament for preventing or treating abnormalities of endochondral ossification-related conditions.

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.

Abstract: A display panel includes a first substrate, an electrode layer, and a display medium layer. The electrode layer is disposed on the first substrate. The display medium layer is disposed on the electrode layer and includes a filler and liquid crystal capsules. The liquid crystal capsules are distributed in the filler, and the filler has a birefringence difference ?n in a range from 0.02 to 0.175.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a fin structure. The semiconductor structure also includes a source/drain structure in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a first contact plug over the source/drain structure. The semiconductor structure also includes a first via plug over the first contact plug. The semiconductor structure also includes a dielectric layer surrounding the first via plug. The first via plug includes a first group IV element and the dielectric layer includes the first group IV element and a second group IV element.

Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a capping layer over a fin of a fin field effect transistor (finFET), where the fin is formed of a material comprising germanium. The method also includes forming a dummy dielectric layer over the capping layer. The method also includes forming a dummy gate over the dummy dielectric layer. The method also includes removing the dummy gate.

Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.

Abstract: A liquid crystal panel includes a substrate and a display medium layer. The display medium layer is located on the substrate. The display medium layer includes multiple first liquid crystal capsules and multiple second liquid crystal capsules. Each of the first liquid crystal capsules includes multiple first liquid crystal molecules. A dielectric anisotropy ?? of the first liquid crystal molecules is greater than 0. A refractive index of the first liquid crystal capsules on the z-axis is greater than refractive indices of the first liquid crystal capsules on the x-axis and on the y-axis. Each of the second liquid crystal capsules includes second liquid crystal molecules. A dielectric anisotropy ?? of the second liquid crystal molecules is greater than 0. A refractive index of the second liquid crystal capsules on the z-axis is smaller than refractive indices of the second liquid crystal capsules on the x-axis and on the y-axis.

Abstract: A method for forming a semiconductor structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes depositing a dopant source layer over the gate structure. The method also includes driving dopants of the dopant source layer into the fin structure. The method also includes removing the dopant source layer. The method also includes annealing the dopants in the fin structure to form a doped region. The method also includes etching the doped region and the fin structure below the doped region to form a recess. The method also includes growing a source/drain feature in the recess.

Abstract: Embodiments disclosed herein relate generally to forming a source/drain region with a high surface dopant concentration at an upper surface of the source/drain region, to which a conductive feature may be formed. In an embodiment, a structure includes an active area on a substrate, a dielectric layer over the active area, and a conductive feature through the dielectric layer to the active area. The active area includes a source/drain region. The source/drain region includes a surface dopant region at an upper surface of the source/drain region, and includes a remainder portion of the source/drain region having a source/drain dopant concentration. The surface dopant region includes a peak dopant concentration proximate the upper surface of the source/drain region. The peak dopant concentration is at least an order of magnitude greater than the source/drain dopant concentration. The conductive feature contacts the source/drain region at the upper surface of the source/drain region.