Patents by Inventor Liang-Yin Chen
Liang-Yin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190288068Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.Type: ApplicationFiled: June 6, 2019Publication date: September 19, 2019Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Maio Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
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Publication number: 20190267471Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.Type: ApplicationFiled: February 28, 2018Publication date: August 29, 2019Inventors: Chia-Ling Chan, Derek Chen, Liang-Yin Chen, Chien-I Kuo
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Publication number: 20190245057Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.Type: ApplicationFiled: April 22, 2019Publication date: August 8, 2019Inventors: Chia-Cheng Chen, Meng-Shu Lin, Liang-Yin Chen, Xiong-Fei Yu, Syun-Ming Jang, Hui-Cheng Chang
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Patent number: 10361094Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.Type: GrantFiled: July 31, 2018Date of Patent: July 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Hao Liu, Tsan-Chun Wang, Liang-Yin Chen, Jing-Huei Huang, Lun-Kuang Tan, Huicheng Chang
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Patent number: 10347762Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.Type: GrantFiled: May 29, 2018Date of Patent: July 9, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Su-Hao Liu, Kuo-Ju Chen, Chun-Hung Wu, Chia-Cheng Chen, Liang-Yin Chen, Huicheng Chang, Ying-Lang Wang
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Patent number: 10347720Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.Type: GrantFiled: October 30, 2017Date of Patent: July 9, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
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Patent number: 10326003Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a first gate spacer is formed over a dummy gate of a fin field effect transistor (finFET). The method also includes performing a carbon plasma doping of the first gate spacer. The method also includes forming a plurality of source/drain regions, where a source/drain region is disposed on opposite sides of the dummy gate. The method also includes removing dummy gate.Type: GrantFiled: March 29, 2017Date of Patent: June 18, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chen, Huicheng Chang, Liang-Yin Chen, Chun-Feng Nieh, Li-Ting Wang, Wan-Yi Kao, Chia-Ling Chan
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Publication number: 20190165099Abstract: Embodiments disclosed herein relate generally to forming a source/drain region with a high surface dopant concentration at an upper surface of the source/drain region, to which a conductive feature may be formed. In an embodiment, a structure includes an active area on a substrate, a dielectric layer over the active area, and a conductive feature through the dielectric layer to the active area. The active area includes a source/drain region. The source/drain region includes a surface dopant region at an upper surface of the source/drain region, and includes a remainder portion of the source/drain region having a source/drain dopant concentration. The surface dopant region includes a peak dopant concentration proximate the upper surface of the source/drain region. The peak dopant concentration is at least an order of magnitude greater than the source/drain dopant concentration. The conductive feature contacts the source/drain region at the upper surface of the source/drain region.Type: ApplicationFiled: November 29, 2017Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng CHEN, Liang-Yin CHEN
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Publication number: 20190157148Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a first contact plug and a first via plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The first contact plug is positioned over the source/drain structure. The first via plug is positioned over the first contact plug. The first via plug includes a first group IV element.Type: ApplicationFiled: June 28, 2018Publication date: May 23, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tung-Po HSIEH, Su-Hao LIU, Hong-Chih LIU, Jing-Huei HUANG, Jie-Huang HUANG, Lun-Kuang TAN, Huicheng CHANG, Liang-Yin CHEN, Kuo-Ju CHEN
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Publication number: 20190157456Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes forming a modified region in the epitaxial structure. The modified region has lower crystallinity than an inner portion of the epitaxial structure and extends along an entirety of an exposed surface of the epitaxial structure. The method also includes forming a semiconductor-metal compound region on the epitaxial structure. All or some of the modified region is transformed into the semiconductor-metal compound region.Type: ApplicationFiled: July 18, 2018Publication date: May 23, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng CHEN, Su-Hao LIU, Kuo-Ju CHEN, Liang-Yin CHEN
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Publication number: 20190131399Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.Type: ApplicationFiled: October 30, 2017Publication date: May 2, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Su-Hao LIU, Huicheng CHANG, Chia-Cheng CHEN, Liang-Yin CHEN, Kuo-Ju CHEN, Chun-Hung WU, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
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Publication number: 20190123181Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a capping layer over a fin of a fin field effect transistor (finFET), where the fin is formed of a material comprising germanium. The method also includes forming a dummy dielectric layer over the capping layer. The method also includes forming a dummy gate over the dummy dielectric layer. The method also includes removing the dummy gate.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Inventors: Chia-Cheng Chen, Huicheng Chang, Liang-Yin Chen
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Patent number: 10269921Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.Type: GrantFiled: November 21, 2016Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Chia-Cheng Chen, Liang-Yin Chen, Xiong-Fei Yu, Syun-Ming Jang, Hui-Cheng Chang, Meng-Shu Lin
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Patent number: 10269656Abstract: A method for semiconductor processing includes forming a first dielectric layer comprising an N-type dopant over a first plurality of fins extending above a first region of a substrate, forming a second dielectric layer comprising a P-type dopant over the first plurality of fins and a second plurality of fins extending above a second region of the substrate, the second dielectric layer overlying the first dielectric layer, and forming an isolation layer between adjacent ones of the first plurality of fins, and between adjacent ones of the second plurality of fins. The method further includes performing an implantation process using a first dopant, the implantation process changing an etching rate of the isolation layer, and recessing the isolation layer, the first dielectric layer, and the second dielectric layer, where after the recessing, the first and the second plurality of fins extend above an upper surface of the isolation layer.Type: GrantFiled: October 20, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsan-Chun Wang, Liang-Yin Chen
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Patent number: 10263091Abstract: A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.Type: GrantFiled: December 14, 2016Date of Patent: April 16, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yee-Chia Yeo, Chih Chieh Yeh, Chih-Hsin Ko, Cheng-Hsien Wu, Liang-Yin Chen, Xiong-Fei Yu, Yen-Ming Chen, Chan-Lon Yang
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Publication number: 20190027473Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a gate structure and a source/drain feature. The gate structure is positioned over a fin structure. The source/drain feature is positioned adjacent to the gate structure. A portion of the source/drain feature embedded in the fin structure has an upper sidewall portion adjacent to a top surface of the fin structure and a lower sidewall portion below the upper sidewall portion. A first curve radius of the upper sidewall portion is different from a second curve radius of the lower sidewall portion in a cross-sectional view substantially along the longitudinal direction of the fin structure.Type: ApplicationFiled: July 18, 2017Publication date: January 24, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng CHEN, Chia-Ling CHAN, Liang-Yin CHEN, Huicheng CHANG
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Patent number: 10177006Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.Type: GrantFiled: February 23, 2017Date of Patent: January 8, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Hao Liu, Tsan-Chun Wang, Liang-Yin Chen, Jing-Huei Huang, Lun-Kuang Tan, Huicheng Chang
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Patent number: 10164066Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a capping layer over a fin of a fin field effect transistor (finFET), where the fin is formed of a material comprising germanium. The method also includes forming a dummy dielectric layer over the capping layer. The method also includes forming a dummy gate over the dummy dielectric layer. The method also includes removing the dummy gate.Type: GrantFiled: July 3, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chen, Huicheng Chang, Liang-Yin Chen
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Publication number: 20180366341Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.Type: ApplicationFiled: July 31, 2018Publication date: December 20, 2018Inventors: Su-Hao Liu, Tsan-Chun Wang, Liang-Yin Chen, Jing-Huei Huang, Lun-Kuang Tan, Huicheng Chang
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Publication number: 20180166341Abstract: A plasma doping process provides conformal doping profiles for lightly doped source/drain regions in fins, and reduces the plasma doping induced fin height loss. The plasma doping process overcomes the limitations caused by traditional plasma doping processes in fin structures that feature aggressive aspect ratios and tights pitches. Semiconductor devices with conformal lightly doped S/D regions and reduced fin height loss demonstrate reduced parallel resistance (Rp) and improved transistor performance.Type: ApplicationFiled: December 13, 2016Publication date: June 14, 2018Inventors: Chia-Ling CHAN, Tsan-Chun Wang, Liang-Yin Chen, Huicheng Chang