Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.

Abstract: The present invention provides a system for selecting a sample phase based on channel capacity. A synchronizer calculates a carrier frequency offset, a sample timing offset, a sampling conversion rate and a frame timing, and counts the candidate sample phases. A digital mixer conducts frequency offset compensation to produce a frequency compensated baseband signal. An interpolator conducts interpolation to compensate and produce an interpolated baseband signal. A digital matched filter performs filtering to produce an over-sampled and filtered baseband signal. A buffer stores the over-sampled and filtered baseband signal. A channel estimator estimates and produces channel frequency responses. A sample phase selector calculates channel capacity corresponding to each candidate sample phase, and selects the one with maximum channel capacity. A down-sampler conducts down-sampling operation to produce the final symbol rate based baseband signal.