Patents by Inventor Liang-Yu (Tom) Chi

Liang-Yu (Tom) Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12242089
    Abstract: A color filter module is provided. The color filter module is arranged on a display panel. The color filter module includes a transparent substrate and a color resist layer. The transparent substrate includes multiple sub-pixel regions arranged in an array. The color resist layer is arranged on the transparent substrate. The color resist layer includes multiple color resist units. The color resist units are respectively arranged across at least two sub-pixel regions, and the color resist units form a staggered array on the transparent substrate.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: March 4, 2025
    Assignee: E Ink Holdings Inc.
    Inventors: Ian French, Po-Yuan Lo, Liang-Yu Lin
  • Patent number: 12235707
    Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides for converting each respective signal to a respective analog voltage to drive a common node; and utilizing a charge storage device coupled to the common node to accumulate the respective analog voltages from the dice, where the accumulated voltage indicates total power consumption of the dice.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: February 25, 2025
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jonathan S. Parry, Stephen L. Miller, Liang Yu
  • Publication number: 20250062778
    Abstract: A processor decompresses a compressed data vector into an original data vector. The processor includes an execution circuit, which receives a decompress instruction that includes two input operands and an output operand. The input operands indicate an address of the compressed data vector in a memory, and the output operand indicates the vector register for storing the original data vector after decompression. The execution circuit executes the decompress instruction to decompress the compressed data vector. When executing the decompress instruction, the execution circuit performs the following operations: read a mask value from the mask register, the mask value being a binary sequence indicating zero positions in the original data vector; generate a selection signal based on the mask value; and generate the original data vector by applying the selection signal to a selection switch that receives the compressed data vector as input.
    Type: Application
    Filed: August 18, 2023
    Publication date: February 20, 2025
    Inventors: Chih-Chun Liu, Liang-Yu Chen, Yao Ting Wang
  • Publication number: 20250058297
    Abstract: The present invention provides a zirconium-based metal-organic framework material and a preparation method therefor and the use thereof, and an adsorption separation device and method. The zirconium-based metal-organic framework material has a chemical structural formula of [C18H6O16Zr3]n, and comprises zirconium and an organic ligand forming a coordination bond with zirconium, wherein the organic ligand is diphenylethyne-3,3?,5,5?-tetracarboxylic acid. The molecular structure of the zirconium-based metal-organic framework material of the present invention is a three-position network structure having a one-dimensional channel; and in the present invention, the size of the one-dimensional channel is accurately controlled by changing the aspect ratio of the organic ligand, such that the zirconium-based metal-organic framework material efficiently separates a hexane isomer by means of a kinetic effect.
    Type: Application
    Filed: December 2, 2022
    Publication date: February 20, 2025
    Inventors: Qihan GONG, Hao WANG, An MA, Jiayu DING, Shang ZHANG, Liang YU, Guangjuan GUO, Yawen BO, Hongyue YU, Kebin CHI
  • Publication number: 20250053039
    Abstract: An E-paper display panel including an E-paper display layer, a first substrate, a pixel array layer, a common electrode layer, and a driving circuit is provided. The first substrate is disposed at a first side of the E-paper display layer. The pixel array substrate is disposed between the first substrate and the E-paper display layer and includes touch electrodes and driving pixels arranged in an array. Each driving pixel includes a first pixel electrode and a second pixel electrode. The touch electrodes, the first pixel electrode, and the second pixel electrode are overlapped with each other. The common electrode layer is disposed at a second side of the E-paper display layer. The first side is opposite to the second side. The driving circuit is in signal communication with the common electrode layer and the pixel array layer. The touch electrodes are individually in signal communication with the driving circuit.
    Type: Application
    Filed: July 11, 2024
    Publication date: February 13, 2025
    Applicant: E Ink Holdings Inc.
    Inventors: Chia-Ming Hsieh, Chi-Mao Hung, Sung-Hui Huang, Chuen-Jen Liu, Liang-Yu Yan, Pei Ju Wu, Po-Chun Chuang, Che-Sheng Chang, Wen-Chung Yang
  • Publication number: 20250043530
    Abstract: The invention discloses an enhanced anti-seismic structure suitable for urban underground comprehensive pipe galleries. Comprising a polygonal frame with an outer frame and an inner frame arranged inside it. Vertex of the inner frame is connected to the bending position inside the outer frame via a support rod. Outer frame has installation grooves for pipe installation, corresponding one-to-one with its sides. The outer frame, located outside the installation groove, can be disassembled to install a limit frame. A limit mechanism for fixing the pipe is installed on the limit frame. The outer frame, positioned outside the installation slot, can be disassembled to install a limit frame. Screwing in a screw drives a lifting block to compress a spring, causing a top block to press against the pipe surface and secure it. The polygonal frame allows for multiple pipes to be installed simultaneously, enhancing overall stability through the support rod connections.
    Type: Application
    Filed: July 1, 2022
    Publication date: February 6, 2025
    Inventors: Xiuling CAO, Muci YUE, Liang YU, Xiaohong QU, Junfeng WANG, Congxu YANG, Anguelov K. A., CASAGLI N., Xinzhi LIU, Zihan FENG, Shuo HAN
  • Publication number: 20250005293
    Abstract: Implementations relate to leveraging large language model(s) (LLMs) and vision language model(s) (VLMs) to facilitate human-to-computer dialogs. In various implementations, one or more digital images may be processed using one or more VLMs to generate VLM output indicative of a state of an environment. An LLM prompt may be assembled based on the VLM output and a natural language input. The LLM prompt may be processed using one or more LLMs to generate content that is responsive to the natural language input. The content that is responsive to the natural language input may subsequently be rendered at one or more output devices.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Tuan Nguyen, Sergei Volnov, William A. Truong, Yunfan Ye, Sana Mithani, Neel Joshi, Alexey Galata, Tzu-Chan Chuang, Liang-yu Chen, Qiong Huang, Krunal Shah, Sai Aditya Chitturu
  • Publication number: 20250004061
    Abstract: A control method for impedance spectrum measurement of a battery is disclosed. The battery outputs a power via a DC-DC converter. The control method includes (i) sending a first signal, wherein the first signal indicates a conduction mode of the DC-DC converter to be set, and the conduction mode includes a discontinuous conduction mode or a critical conduction mode, (ii) receiving a current measurement value and a voltage measurement value at an output end of the battery, and (iii) calculating an impedance spectrum of the battery based on the received current measurement value and the received voltage measurement value. A control device and a system for impedance spectrum measurement of a battery, a computer-readable storage medium, a computer program product, a vehicle electronic control unit, and a vehicle is also disclosed.
    Type: Application
    Filed: October 13, 2022
    Publication date: January 2, 2025
    Inventors: Guozhen Zhou, Peng Gao, Liang Yu, Xiaoyun Zang, Xudan Liu, Junbing Tao
  • Publication number: 20240395904
    Abstract: A semiconductor device includes a source region, a drain region, a gate structure, a first gate spacer, and a second gate spacer. The source region and the drain region are in a substrate. The gate structure is laterally between the source region and the drain region. The first gate spacer is on a first sidewall of the gate structure. The second gate spacer is on a second sidewall of the gate structure. The first gate spacer has more layers than the second gate spacer.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Feng HAN, Lei SHI, Hung-Chih TSAI, Liang-Yu SU, Hang FAN
  • Publication number: 20240371926
    Abstract: A method includes: receiving the semiconductor device, wherein the semiconductor device includes: a well region; a doped region; a plurality of gate electrodes; a plurality of source regions; and a plurality of drain regions, wherein the plurality of gate electrodes, the plurality of source region and the plurality of drain regions form a plurality of transistors; and a bulk region disposed in the doped region. A first distance measured between a first transistor of the plurality of transistors and the bulk region is greater than a second distance measured between a second transistor of the plurality of transistors and the bulk region. The method further includes: applying a first voltage to the plurality of drain regions, wherein a first avalanche current generated around the first transistor and shunted through the bulk region is greater than a second avalanche current generated around the second transistor and shunted through the bulk region.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 7, 2024
    Inventors: LIANG-YU SU, FU-YU CHU, MING-TA LEI, RUEY-HSIN LIU, YU-CHANG JONG, NAN-YING YANG, PO-YU CHIANG, YU-TING WEI
  • Publication number: 20240366809
    Abstract: An inhibitor of a prostate specific membrane antigen and a pharmaceutical use thereof. Specifically, the present solution belongs to the field of radiopharmaceuticals and relates to a compound represented by formula (IV) or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: September 1, 2022
    Publication date: November 7, 2024
    Inventors: Mengzhe WANG, Shunguang ZHOU, Liang YU, Lidong WANG, Libo ZHAO, Jiyun SUN, Feihu GUO, Xin LI
  • Publication number: 20240344541
    Abstract: A securing clip includes: an enclosure body including a first end, a second end, and one or more sidewalls that extend between the first end and the second end; one or more fragment module securing tangs extending, from one or more of the sidewalls, into the cavity such that when at least a portion of the fragment module is placed within the cavity, at least a portion of the fragment module securing tang is designed to engage with the fragment module and prevents and/or impedes removal of at least a portion of the fragment module from the cavity; and one or more substrate securing tangs extending from the enclosure body and away from the cavity, each substrate securing tang designed to prevent and/or impede removal of the securing clip when the securing clip is placed into a substrate aperture defined within the substrate
    Type: Application
    Filed: December 22, 2023
    Publication date: October 17, 2024
    Applicant: Reefgen Inc.
    Inventors: Jonathan Pompa, David Solomon, Abhimanyu Belani, Liang Yu Chi
  • Patent number: 12112230
    Abstract: An electronic paper display, comprising a carrier device, a memory, a display panel, a sensing device and a processing device. The carrier device is arranged on a logistics box. The memory is arranged on the carrier device, and is configured to store a logistics data. The display panel is arranged on the carrier device, and is configured to generate a control voltage according to the logistics data to adjust a plurality of positions of a plurality of electrophoretic particles. The sensing device comprises at least one sensor, and is configured to sense at least one state parameter of the logistics box to generate at least one sensing signal. The processing device is coupled to the memory, the display panel and the sensing device, and is configured to send the at least one sensing signal through wireless transmission technology.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: October 8, 2024
    Assignee: E Ink Holdings Inc.
    Inventors: Chuen Jen Liu, Liang Yu Yan, Jia Hong Xu, Zhone Yang Wu
  • Publication number: 20240332411
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer over a base substrate and an active layer over the channel layer. A source and a drain are over the active layer. A gate is over the active layer and laterally between the source and the drain. A dielectric is over the active layer and laterally surrounds the source, the drain, and the gate. A cap structure laterally contacts the source and is disposed laterally between the gate and the source. The source vertically extends to a top of the cap structure.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Inventors: Ming-Cheng Lin, Chen-Bau Wu, Chun Lin Tsai, Haw-Yun Wu, Liang-Yu Su, Yun-Hsiang Wang
  • Publication number: 20240331141
    Abstract: A method and an electronic device are used to estimate osteoporosis. The method includes the following steps. An X-ray image is obtained. The X-ray image is input into a first convolutional neural network model to generate a bone probability heatmap of the X-ray image. A bone density estimation value is estimated based on the bone probability heatmap, the X-ray image, and a second convolutional neural network model.
    Type: Application
    Filed: May 7, 2023
    Publication date: October 3, 2024
    Applicant: Acer Incorporated
    Inventor: Liang-Yu Ke
  • Publication number: 20240324256
    Abstract: A method for preparing a hole transport layer of a perovskite solar cell, comprises S11, providing a conductive substrate; and S12: doping silver, gallium, selenium and sulfur with each other on the conductive substrate to obtain a hole transport layer. The present disclosure further provides a hole transport layer of a perovskite solar cell and a perovskite solar cell.
    Type: Application
    Filed: March 19, 2024
    Publication date: September 26, 2024
    Inventors: WEI-CHAO CHEN, LIANG-YU CHEN, HONG-ZHENG LAI, TSENG-LUNG CHANG
  • Patent number: 12100757
    Abstract: In some embodiments, the present disclosure relates to a method of forming a high electron mobility transistor (HEMT) device. The method includes forming a passivation layer over a substrate. A source contact and a drain contact are formed within the passivation layer. A part of the passivation layer is removed to form a cavity. The cavity has a lower portion formed by a first sidewall and a second sidewall of the passivation layer and an upper portion formed by the first sidewall of the passivation layer and a sidewall of the source contact. A gate structure is formed within the passivation layer between the drain contact and the cavity. A cap structure is formed within the cavity.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: September 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Cheng Lin, Chen-Bau Wu, Chun Lin Tsai, Haw-Yun Wu, Liang-Yu Su, Yun-Hsiang Wang
  • Patent number: 12091454
    Abstract: A humanized anti-neurotensin receptor 1 (NTSR1) antibody or an antigen-binding fragment thereof. Also, a method for treating, prophylactic treating and/or preventing diseases and/or disorders caused by or related to NTSR1 activity and/or signaling, and a method or kit for detecting NTSR1 in a sample.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: September 17, 2024
    Assignees: DEVELOPMENT CENTER FOR BIOTECHNOLOGY, NATIONAL HEALTH RESEARCH INSTITUTES
    Inventors: Cheng-Chou Yu, Shu-Ping Yeh, Chao-Yang Huang, Szu-Liang Lai, Shih-Liang Hsiao, Mei-Ling Hou, Tzung-Jie Yang, Wei-Ting Sun, Liang-Yu Hsia, Andrew Yueh, Chiung-Tong Chen, Ren-Huang Wu, Pei-Shan Wu, Han-Shu Hu, Tzu-Chin Wu, Jia-Ni Tian
  • Patent number: 12084766
    Abstract: In an embodiment, an apparatus includes: a susceptor including substrate pockets; a gas injector disposed over the susceptor, the gas injector having first process regions, the gas injector including a first gas mixing hub and first distribution valves connecting the first gas mixing hub to the first process regions; and a controller connected to the gas injector and the susceptor, the controller being configured to: connect a first precursor material and a carrier gas to the first gas mixing hub; mix the first precursor material and the carrier gas in the first gas mixing hub to produce a first precursor gas; rotate the susceptor to rotate a first substrate disposed in one of the substrate pockets; and while rotating the susceptor, control the first distribution valves to sequentially introduce the first precursor gas at each of the first process regions as the first substrate enters each first process region.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chang Chang, Meng-Yin Tsai, Tung-Hsiung Liu, Liang-Yu Yeh, Chun-Yi Lee, Kuo-Hsi Huang
  • Publication number: 20240290396
    Abstract: Methods, systems, and devices for power management associated with memory and a controller are described. A memory system performs a power management operation that accounts for power usage by any combination of application specific integrated circuits (ASICs) and memory arrays. The power management operation includes multiple logical unit numbers (LUNs) assigned to a single ASIC, which increases a quantity of bits for communicating a power usage. An ASIC included in a memory system may utilize twice as many bits for communicating power usage information when compared to a NAND array. As part of the power management operation, an ASIC may transmit, to a controller, a first set of bits indicating a power usage of the ASIC, a first subset of the set of bits transmitted during a first instance of a token ring and a second subset of the set of bits transmitted during a second instance of the token ring.
    Type: Application
    Filed: February 16, 2024
    Publication date: August 29, 2024
    Inventors: Liang Yu, Jonathan S. Parry, Tal Sharifie