Abstract: Embodiments provide an integrated circuit structure and a memory, and relate to the field of semiconductor memory technologies. The integrated circuit structure includes: a pad region including a plurality of signal pads arranged along a target direction; and a first circuit region arranged on one side of the pad region. The first circuit region includes a plurality of signal input circuit modules arranged along the target direction and correspondingly connected to the plurality of signal pads respectively. Each of the plurality of signal input circuit modules is configured to implement a sampling operation of an input signal and write a sampling result into a storage array. A size of the first circuit region along the target direction is smaller than that of the pad region along the target direction. According to the embodiments, the performance of a write operation can be improved for the memory.

Abstract: An acrylate based photopolymer with high yellowing resistance, excellent photo sensitivity, high toughness, and high glass transition temperature, methods of preparation and used thereof, and solders comprising the same.

Abstract: A driving circuit, including: a pull-up transistor and a pull-down transistor, where a first terminal of the pull-up transistor is connected with a power source, a second terminal of the pull-up transistor is connected with a first terminal of the pull-down transistor to together output a driving signal, and a second terminal of the pull-down transistor is connected to ground; and a control circuit connected with a control terminal of the pull-up transistor and/or the pull-down transistor respectively and configured to control the on or off switching of the pull-up transistor and/or the pull-down transistor so as to change the driving signal. The pull-up transistor and the pull-down transistor are not switched on at the same time under the control of the control circuit.

Abstract: A model update system, which may be applied to the network control field, includes a site analysis device and a first analysis device. The site analysis device is configured to: receive a first model sent by the first analysis device; train the first model by using a first training sample to obtain a second model, where the first training sample includes first feature data of a network device in a site network corresponding to the site analysis device; obtain differential data between the first model and the second model; and send the differential data to the first analysis device. The first analysis device is configured to: send the first model to the site analysis device; receive the differential data sent by the site analysis device; and update the first model based on the differential data to obtain a third model.

Abstract: An alarm log compression method, apparatus, system, and a storage medium are provided. The method includes: obtaining a historical alarm log set generated by a first network device; dividing the historical alarm log set into a plurality of historical alarm log subsets based on a generation time stamp of a historical alarm log in the historical alarm log set, where all historical alarm logs in each historical alarm log subset are consecutive in a time sequence; determining a correspondence between an alarm type in the historical alarm log set and the plurality of historical alarm log subsets; performing clustering processing on the alarm types in the historical alarm log set based on the correspondence, to generate at least one association rule; and compressing to-be-processed alarm logs based on the at least one association rule, to obtain an alarm log whose alarm type is a root cause alarm type.

Abstract: Embodiments of the present disclosure provide methods and apparatuses for resource scheduling. A method at a base station comprises determining a passive interference cancellation capability of a User Equipment (UE) having a passive interference issue. The passive interference is coupled into a receive path of the UE from a transmission of at least one signal through a transmit path of the UE. The method further comprises scheduling at least one uplink resource for the UE based on the passive interference cancellation capability.

Abstract: A receptacle connector for mating with a plug connector having a mating tongue and a latch thereof, includes an insulative housing defining a mating slot extending along a longitudinal direction to receive the mating tongue of the plug connector, and an outer metallic shield defining an upper space to receive the latch of the plug connector, and a lower space communicatively below the upper space to receive the housing. A plurality of contacts are disposed in the housing to mechanically and electrically connect to the mating tongue. An inner metallic shield is attached upon the upper wall of the housing to separate the upper space and the lower space from each other in a vertical direction.

Abstract: A safety belt automatic adjustment apparatus includes a safety belt buckle fastening assembly, a safety belt retractor and a linking component. The safety belt buckle fastening assembly is rotatably connected to a seat body of a child safety seat and for connecting with a safety belt buckle. The safety belt retractor is used for retracting a safety belt, and the safety belt retractor includes a restraining assembly for restraining a movement of the safety belt in a predetermined direction. The linking component is installed between the safety belt buckle fastening assembly and the safety belt retractor, and the safety belt buckle fastening assembly rotates to drive the linking component and the restraining assembly, so as to restrain or release the safety belt winding around the safety belt retractor. The safety belt automatic adjustment apparatus has advantages of automatic adjustment for the safety belt, simple structure, convenient operation and enhanced safety.

Abstract: A memory device and its addressing method are disclosed. The memory device includes: an input module for receiving an input signal including an access address, a command, and a decoding selection instruction; a memory array including memory blocks, each having memory units arranged in an array; and a control module including memory block local control units, which respectively connected to one of the memory blocks in one-to-one correspondence. The memory block local control unit includes: at least one decoding unit, which performs redundant decoding or normal decoding to the input signal. The input of the decoding unit is coupled to the input module and the output is coupled to one of the memory units. The device further includes a selection module; the input of the selection module is coupled to the input module, and the output is coupled to the decoding unit. The addressing efficiency of the memory device is improved.

Abstract: A messenger RNA (mRNA) vaccine has emerged as a promising direction to combat the COVID-19 pandemic. This requires an mRNA sequence that is stable and highly productive in protein expression, features to benefit from greater mRNA secondary structure folding stability and optimal codon usage. Sequence design remains challenging due to the exponentially many synonymous mRNA sequences encoding the same protein. The present disclosure presents embodiments of a linear-time approximation (LinearDesign) reducing the design to an intersection between a Stochastic Context Free Grammar (SCFG) and a Deterministic Finite Automaton (DFA). Embodiments of the LinearDesign may implement an mRNA sequence design using much reduced time with very limited loss. Various methodologies, e.g., finding alternative sequences based on k-best parsing or directly incorporating codon optimality, are presented for incorporating the codon optimality into the design.

Abstract: A memory device and its addressing method are disclosed. The memory device includes: an input module for receiving an input signal including an access address, a command, and a decoding selection instruction; a memory array including memory blocks, each having memory units arranged in an array; and a control module including memory block local control units, which respectively connected to one of the memory blocks in one-to-one correspondence. The memory block local control unit includes: at least one decoding unit, which performs redundant decoding or normal decoding to the input signal. The input of the decoding unit is coupled to the input module and the output is coupled to one of the memory units. The device further includes a selection module; the input of the selection module is coupled to the input module, and the output is coupled to the decoding unit. The addressing efficiency of the memory device is improved.

Abstract: This application provides a method for determining an access device type, a device, and a system. An access device type is determined by obtaining one or more packet pairs and a time difference of each packet pair. Each packet pair includes a first packet and a second packet, where the second packet is a response to the first packet, and the one or more packet pairs pass through a same access device. Based on this solution, maintenance manpower required for determining an access device type can be reduced, and O&M personnel management complexity of operators or service providers can be reduced.

Abstract: A vehicular vision system includes a camera disposed at an in-cabin side of a windshield of a vehicle and viewing forward of the vehicle. The vehicular vision system, responsive at least in part to image processing of multiple frames of captured image data, detects an object present exterior of the vehicle that is moving relative to the vehicle. The system, when the vehicle is moving, and based at least in part to received vehicle motion data indicative of motion of the vehicle when the vehicle is moving and image processing of multiple frames of captured image data, (i) estimates object trajectory of the detected object based at least in part on corresponding object features present in multiple frames of image data captured by the camera and (ii) determines motion of the detected object relative to the moving vehicle based on the estimated object trajectory.

Abstract: Disclosed is a low power consumption switching circuit with voltage isolation function for a PMOS transistor bulk, including a bulk voltage switching control unit, a bulk voltage switching unit, a first voltage input terminal, a second voltage input terminal, and a bulk voltage output terminal. The bulk voltage switching control unit includes a plurality of PMOS transistors and weak pull-down devices, and is configured to generate a control signal to control the bulk voltage switching unit to make the bulk voltage output terminal to be connected to a higher potential between the first voltage input terminal and the second voltage input terminal. The bulk voltage switching unit includes a plurality of PMOS transistors, and is configured to connect bulks of the PMOS transistors to the higher potential between the first voltage input terminal and the second voltage input terminal. Each of the PMOS transistors is a low-withstand-voltage device.

Abstract: The present disclosure provides a method of manufacturing a surface nanotube array of a laser-melted stainless steel, including a step of an anodic oxidation treatment on the stainless steel, which includes performing the anodic oxidation treatment on the stainless steel by applying a voltage between the stainless steel as an anode and a graphite as a cathode in a solution formed by using sodium dihydrogen phosphate, perchloric acid, and ethylene glycol as a solute, and deionized water as a solvent.

Abstract: The present application discloses a composition of a butyrate or a derivative thereof and benzoic acid, preparation method and use as a feedstuff additive thereof, wherein the composition comprises 5 wt % to 50 wt % of the butyrate or the derivative of butyric acid, and 50 wt % to 95 wt % of the benzoic acid or benzoate. The benzoate and butyrate dissociate into acidic molecules when they enter into animals' bodies. The butyric acid stimulates parietal cells to grown and the parietal cells produce hydrochloric acid, which thereby reduces the pH value in the stomach. Benzoic acid can inhibit facultative anaerobes such as Lactobacillus and butyric acid-producing anaerobic bacteria in the stomach, rendering the two floras become predominant microflora, and therefore produce more endogenous organic acids such as lactic acid and butyric acid. These acids are beneficial to gastrointestinal health and animal growth. As a result, a synergy effect of the two components in the composition is achieved.

Abstract: A fault locating method includes: receiving, by a first network device, a fault information packet flooded by another network device in a network, where each fault information packet includes statistical information about an interior gateway protocol packet of the network device sending the fault information packet, and the statistical information of each network device includes a statistical result on one or more key performance indicators KPIs of the network device; and determining, based on statistical information of the first network device and the statistical information of the another network device, a network device on which a fault occurs in the network. According to the method, the fault information packet flooded by the network device is received, so that information required for fault locating, that is, the KPI of the network device, can be quickly collected. This facilitates a fault locating process and reduces a fault locating time.

Abstract: A receptacle connector for mating with a plug connector having a mating tongue and a latch thereof, includes an insulative housing defining a mating slot extending along a longitudinal direction to receive the mating tongue of the plug connector, and an outer metallic shield defining a primary space to receive the housing and a secondary space communicatively beside the primary space to receive the latch of the plug connector. A plurality of contacts are disposed in the housing to mechanically and electrically connect to the mating tongue. An inner metallic shield is attached upon a long side of the housing to separate the primary space and the secondary space from each other in a transverse direction perpendicular to the longitudinal direction.

Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.

Abstract: A data packet sending method, a network device, a control device, and a network system includes receiving a first data packet sent by a first device, where a packet header of the first data packet includes a first sequence number marker sequence, a first position marker sequence, a first accumulated value, and a verification value; obtaining a second data packet, where a packet header of the second data packet includes a second sequence number marker sequence, a second position marker sequence, a second accumulated value, and the verification value; and sending the second data packet to a second device.