Abstract: Embodiments of this application relate to the field of storage technologies, and disclose a data backup method and a terminal, to back up user data in a terminal when the terminal cannot be used. A specific solution is as follows: A terminal includes a first data partition, and the first data partition supports to start an operating system when the terminal is powered on. The terminal starts the operating system by using a second data partition after detecting a power-on failure of the terminal or detecting a preset operation of a user. The second data partition is a blank data partition. After the operating system is successfully started, the terminal transmits user data in the first data partition to a first storage medium. The first storage medium is located outside the terminal and is connected to the terminal.

Abstract: A novel polymer mixture having fast drying time, a multilayer article comprising at least one layer of the dried polymer mixture and having good mechanical properties, and a method of preparing the multilayer article.

Abstract: An optical communication system that comprises a transmitter adapted to generate a signal by modulating a transmission data as low power consumption symbols of an amplitude modulation format and a monitoring data (MD) as high power consumption symbols of the amplitude modulation format, the MD comprising at least one transmitter parameter and/or at least one receiver parameter of communicating the transmission data. A binary logarithm of a total number of the low power consumption symbols and the high power consumption symbols is a non-integer.

Abstract: Embodiments provide a write operation circuit, a semiconductor memory, and write operation method. The write operation circuit includes: a data determination module that determines whether to flip an input data of the semiconductor memory depending on the number of high data bits in the input data so as to generate a flip flag data and a first intermediate data; a data buffer module that determines whether to flip a global bus according to a second intermediate data, where the second intermediate data is an inverted data of the first intermediate data; a data receiving module that decodes the global bus data according to the flip flag data and writes the decoded data into a memory bank of the semiconductor, where the decoding including determining whether to flip the global bus data; and a precharge module that sets the initial state of the global bus to low.

Abstract: Embodiments provide a write operation circuit, a semiconductor memory, and a write operation method. The write operation circuit includes a serial-to-parallel conversion circuit, a data buffer, a DBI decoder, and a precharge module. The serial-to-parallel conversion circuit performs serial-to-parallel conversion on first DBI data of a DBI port to generate second DBI data for transmission via a DBI signal line and generates input data of the data buffer according to the second DBI data and input data of a DQ port. The data buffer determines, according to the input data of the data buffer, whether to invert the global bus. The DBI decoder receives the second DBI data, decodes the global bus data and writes the decoded global bus data into the memory bank, where the decoding comprises determining whether to invert the global bus data. The precharge module sets an initial state of the global bus to Low.

Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a DBI encoder configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of low data in the read data to output global bus data for transmission through a global bus and DBI data for transmission through a DBI signal line, wherein a DBI port is configured to receive the DBI data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the global bus data to generate output data of the DQ port; a data buffer module connected to the memory bank through the global bus; and a precharge module connected to a precharge signal line and configured to set an initial state of the global bus to High.

Abstract: Embodiments provide a write operation circuit, a semiconductor memory, and a write operation method. The write operation circuit includes: a data determination module that determines whether to flip the current input data according to the previous depending on the number of changed data bits between the previous input data and the current input data of the semiconductor memory so as to generate a flip flag data and an intermediate data; a data buffer module that is used to determine an initial state of a global bus according to an enable signal and the intermediate data; and a data receiving module that receives the global bus data on the global bus, and receives the flip flag data through the flip flag signal line, and that is used to decode the global bus data according to the flip flag data, and write the decoded data into a memory block of the semiconductor.

Abstract: This application belongs to the field of service orchestration and discloses a service orchestration method and apparatus, and a service provisioning method and apparatus. The method includes: obtaining a service template; obtaining a service identity, a service attribute, and a service policy that are entered by an operator and a default service parameter; filling in the options of the service template with the service attribute and the service policy that are entered by the operator and the default service parameter; associating the service template that is filled in with the service identity; and storing the service template that is associated with the service identity in a service type library, and publishing the service template to the user.

Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a data determination module configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line; a data receiving module configured to determine whether to invert the global bus data according to the inversion flag data to output cache data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the cache data to generate output data of the DQ port; and a precharge module configured to set an initial state of the global bus to Low.

Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a data determination module configured to read data from the memory bank, and determine, according to the number of bits of a data change between previous read data and current read data, whether to invert the current read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line; a data receiving module configured to determine whether to invert the global bus data according to the inversion flag data to output cache data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the cache data to generate output data of a DQ port; and a data buffer module configured to determine an initial state of the global bus according to enable signal and current read data.

Abstract: Embodiments provide an integrated circuit structure and a memory, and relate to the field of semiconductor memory technologies. The integrated circuit structure includes: a pad region including a plurality of signal pads arranged along a target direction; and a first circuit region arranged on one side of the pad region. The first circuit region includes a plurality of signal input circuit modules arranged along the target direction and correspondingly connected to the plurality of signal pads respectively. Each of the plurality of signal input circuit modules is configured to implement a sampling operation of an input signal and write a sampling result into a storage array. A size of the first circuit region along the target direction is smaller than that of the pad region along the target direction. According to the embodiments, the performance of a write operation can be improved for the memory.

Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a DBI encoder configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through a global bus and DBI data for transmission through a DBI signal line, a DBI port being configured to receive the DBI data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the global bus data to generate output data of the DQ port; a data buffer module connected to the memory bank through the global bus; and a precharge module connected to a precharge signal line and configured to set an initial state of the global bus to Low.

Abstract: Embodiments provide a write operation circuit, a semiconductor memory, and a write operation method. The write operation circuit includes: a data determination module, a data buffer, a data receiving module, and a precharge module. The data determination module determines, according to a number of low-level bits in input data of a semiconductor memory, whether to invert the input data to generate inversion flag data and first intermediate data. The data buffer determines, according to second intermediate data, whether to invert a global bus, where the second intermediate data is inverted data of the first intermediate data. The data receiving module decodes global bus data according to the inversion flag data and writes the decoded data into the memory bank, where the decoding includes determining whether to invert the global bus data. The precharge module sets an initial state of the global bus to high.

Abstract: An address identification method, apparatus, system, storage medium, a processor and a terminal are disclosed. In an embodiment, the method includes: defining a screening library including at least one expected attribute value describing an expected state value of a device parameter to be addressed in an operating mode of an industrial device; acquiring a data group including an actual state value generated in the operating mode and an address where the actual state value is stored; for each address, extracting an actual attribute value, stored in the address, of the actual state value; comparing the actual attribute value with the expected attribute value, determining the actual state value corresponding to the actual attribute value which complies with the expected attribute value, and determining, from the data group, an address corresponding to the selected actual state value; and taking the selected address as a final address and outputting same.

Abstract: Entity resolution techniques for matching entity records from different data sources are provided. In one technique, an entity record from a source database is identified along with multiple data items included therein. Each data item corresponds to an attribute of multiple source attributes. For one of the data items that corresponds to a first source attribute, multiple target attributes are identified. A first query is generated that includes the data items and associates the data item with each of the multiple target attributes. A second query that is different than the first query is also generated. Two searches are performed of a target database: one based on the first query and the other based on the second query. A scoring model generates multiple scores, one for each search result. It is determined whether the entity record matches an entity record in the target database based on the set of scores.

Abstract: A signal transmission system comprises: a power supply, a power sourcing device and a powered device connected to each other through a coaxial cable; the power sourcing device comprises a first active inductor module for receiving a DC signal transmitted by the power supply, and transmitting the DC signal to the powered device through the coaxial cable, a first capacitor module for receiving a superposed signal transmitted through the coaxial cable, and transmitting the superposed signal to a signal processing module; and the powered device comprises a second active inductor module for receiving, through the coaxial cable, the DC signal, and transmitting the DC signal to a signal acquiring module for acquiring a superposed signal, a second capacitor module for transmitting the superposed signal to the power sourcing device through the coaxial cable, and the signal acquiring module is for transmitting the superposed signal to the second capacitor module.

Abstract: A vehicular vision system includes a camera disposed at an in-cabin side of a windshield of a vehicle and viewing forward of the vehicle. The control, responsive at least in part to image processing by an image processor of multiple frames of captured image data, detects an object present exterior of the equipped vehicle that is moving relative to the equipped vehicle. The control receives vehicle motion data indicative of motion of the vehicle when the vehicle is moving. The control, responsive at least in part to the received vehicle motion data, and via image processing of multiple frames of captured image data, determines motion of the detected object relative to the moving vehicle by (i) determining corresponding object points in at least two frames of captured image data and (ii) estimating object motion trajectory of the detected object based at least in part on the determined corresponding object points.

Abstract: A current limiting circuit, comprising a switching circuit and a voltage stabilizing circuit. The switching circuit is separately connected to a voltage input terminal VIN and a voltage output terminal VOUT, and used for transmitting an input voltage to the voltage output terminal VOUT from the voltage input terminal VIN; and the voltage stabilizing circuit is separately connected to the switching circuit, the voltage input terminal VIN, and the voltage output terminal VOUT, used for controlling an output current to reduce together with the switching circuit when the output current of the voltage output terminal VOUT is increased and the output current is less than a preset output current, and further used for controlling the output current to be zero together with the switching circuit when the output current of the voltage output terminal VOUT is greater than or equal to the preset output current.