Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Abstract: Provided is a system for analyzing features associated with entities using an embedding tree, the system including at least one processor programmed or configured to receive a dataset associated with a plurality of entities, wherein the dataset comprises a plurality of data instances for a plurality of entities. The processor may be programmed or configured to generate at least two embeddings based on the dataset and determine split criteria for partitioning an embedding space of at least one embedding tree associated with the dataset based on feature data associated with an entity and embedding data associated with the at least two embeddings. The processor may be programmed or configured to generate at least one embedding tree having a plurality of nodes based on the split criteria. Methods and computer program products are also provided.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.

Abstract: A method includes forming a first transistor stack over a substrate. The first transistor stack includes: a first transistor of a first conductivity type, and a second transistor of a second conductivity type different from the first conductivity type. The second transistor is above the first transistor. A plurality of first conductive lines is formed in a first metal layer above the first transistor stack. The plurality of first conductive lines includes, over the first transistor stack, a power conductive line configured to route power to the first transistor stack, one or more signal conductive lines configured to route one or more signals to the first transistor stack, and a shielding conductive line configured to shield the routed one or more signals. The one or more signal conductive lines are between the power conductive line and the shielding conductive line.

Abstract: A semiconductor device, includes a first metal layer, a second metal layer, and at least one conductive via. The first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction. The second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. The at least one conductive via connects the first conductor and the second conductor through the third conductor. The semiconductor device further includes at least one of a first gate electrode that extends in the second direction and is connected to the first conductor, or a drain/source contact that extends in the second direction and is connected to the second conductor.

Abstract: An integrated circuit is provided and includes first and second gates arranged in first and second layers, wherein the first and second gates extend in a first direction; a first insulating layer interposed between the first and second gates, wherein the first insulating layer, a first portion of the first gate, and a first portion of the second gate overlap with each other in a layout view; a cut layer, different from the first insulating layer, disposed on a second portion of the first gate; a first via passing through the cut layer and coupled to the second portion of the first gate; and a second via overlapping the first portion of the first gate and the first portion of the second gate, and coupled to the second gate. The first and second vias are configured to transmit different control signals to the first and second gates.

Abstract: A device includes a plurality of tracks, wherein at least one of the plurality of tracks comprises a first power rail for a first voltage. The device further includes a first via in electrical contact with the power rail. The device further includes a first contact in electrical contact with the first via. The device further includes a first transistor in electrical contact with the first contact. The device further includes a second transistor in electrical isolation with the first transistor. The device further includes a second contact in electrical contact with the second transistor. The device further includes a second via in electrical contact with the second contact. The device further includes a second power rail in electrical contact with the second via, wherein the second power rail is configured to carry a second voltage.

Abstract: A semiconductor device including a first oxide definition (OD) strip doped by a first-type dopant in a first doping region defining an active region of a first Metal-Oxide Semiconductor (MOS); a second OD strip doped by a second-type dopant in a second doping region and a third doping region, the second doping region defining an active region of a second MOS and the third doping region defining a body terminal of the first MOS, wherein the second OD is parallel to the first OD strip; and a first dummy OD strip, wherein a boundary between the second doping region and the third doping region is formed over the first dummy OD strip; wherein the first-type dopant is different from the second-type dopant.

Abstract: An integrated circuit includes a set of active regions, a first contact, a set of gates, a first and second conductive line and a first and second via. The set of active regions extends in a first direction, and is on a first level. The first contact extends in a second direction, is on a second level, and overlaps at least a first active region. The set of gates extends in the second direction, overlaps the set of active regions, and is on a third level. The first conductive line and the second conductive line extend in the first direction, overlap the first contact, and are on a fourth level. The first via electrically couples the first contact and the first conductive line together. The second via electrically couples the first contact and the second conductive line together.

Abstract: A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.

Abstract: A method of forming a semiconductor device includes forming first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction, and correspondingly overlap and electrically couple to a doped region. The method further includes forming a via-to-via (V2V) rail which extends in a second direction angled with respect to the first direction, wherein the V2V rail overlaps at least of the first MD contact structure or the third MD contact structure. The method further includes forming a first via-to-MD (VD) structure over, and electrically coupled to, the first MD contact structure and the V2V rail. The method further includes forming a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and is electrically coupled to the first VD structure.

Abstract: A method is provided and includes operations below: forming a multilayer stack, wherein the multilayer stack includes multiple first semiconductor layers and multiple second semiconductor layers that are alternately stacked; forming a first source region and a first drain region on opposing sides of a first portion of the multilayer stack and forming a second source region and a second drain region on opposing sides of a second portion of the multilayer stack; removing the second semiconductor layers in the multilayer stack; forming a first gate region, corresponding to a first transistor, over the first portion of the multilayer stack; forming a first insulating layer above the first gate region; and forming a second gate region, corresponding to a second transistor, above the first insulating layer and over the second portion of the multilayer stack.

Abstract: An integrated circuit includes a set of active regions, a first set of contacts, a set of gates, a first set of power rails and a first set of vias. The set of active regions extends in a first direction. The first set of contacts overlaps the set of active regions, and a first and a second cell boundary of the integrated circuit that extends in a second direction. The set of gates extends in the second direction, overlaps the set of active regions, and is between the first and second cell boundary. The first set of power rails extends in the first direction, and overlaps at least the first set of contacts. The first set of vias electrically couples the first set of contacts and the first set of power rails together. The set of active regions extend continuously through the first cell boundary and the second cell boundary.

Abstract: A method for fabricating a fly-eye lens comprises the following steps: preparing a fly-eye mold (1) and a fly-eye base (2), wherein the fly-eye mold (1) is provided with a hemispherical recess that matches the fly-eye base (2), the bottom of the hemispherical recess is provided with a number of arrayed concave surfaces, the fly-eye base (2) has a hemispherical structure, mini-channels (3) penetrating through a spherical surface and a flat surface of the fly-eye base (2) are arranged inside the fly-eye base, and the arrangement of openings of the mini-channels (3) at the spherical surface is in consistency with that of the concave surfaces inside the fly-eye mold (1); and installing the fly-eye base (2) in the fly-eye mold (1) in a fitted manner, injecting polydimethylsiloxane through the mini-channels (3) of the fly-eye base (2), curing the polydimethylsiloxane, and removing the fly-eye base (2) from the fly-eye mold (1) to obtain the fly-eye lens.

Abstract: The present disclosure discloses a travel pillow, including: a lashing strap, a pillowcase, and an inner support. The inner support is received in the pillowcase; a first end of the lashing strap is fixedly connected to the inner support through the pillowcase; a second end of the lashing strap opposite to the first end is detachably connected to the first end; the inner support includes a first support and a second support; and the first support and the second support are configured to be elastically adaptively connected to each other in a supporting direction. The travel pillow can absorb vibration, achieve buffering, and avoid poor experience or the risk of falling caused by the vibration or posture adjustment.

Abstract: Embodiments of the present invention provide a signal processing method and apparatus. The method includes: performing M-way filtering on an input signal to obtain M filtered signals, performing extraction on M filtered signals separately to obtain M extracted signals, performing fast Fourier transform (FFT) on the M extracted signals separately to obtain M frequency-domain signals, and finally determining output signals according to the M frequency-domain signals. According to the embodiments of the present invention, signal filtering and extraction are performed and then FFT is performed.

Abstract: The present disclosure provides a data format conversion apparatus and method, and a buffer chip. The data format conversion apparatus is disposed on the buffer chip in a memory; a control module is disposed for sending a control instruction to a conversion module when obtaining a data copy command; and a conversion module is disposed for completing data format conversion and storage address mapping on to-be-converted data according to the received control instruction. In this way, a prior-art problem of additionally occupying computing resources and computation time of an accelerated computation unit due to a data format conversion unit disposed in the accelerated computation unit is avoided, the amount of data transmission between a main memory and a device memory is reduced without additionally occupying computing resources, and the computation precision is ensured while the computation efficiency is improved.

Abstract: Embodiments of the present invention disclose an electronic device and a graphics processing unit card, which can improve data input and output capabilities. The electronic device includes a graphics processing unit card and a mainboard. The graphics processing unit card includes a main chip and M first PCIe interfaces electrically connected to the main chip, where M is an integer greater than or equal to 2. The mainboard includes a processing unit and M second PCIe interfaces connected to the processing unit, and the M second PCIe interfaces are respectively connected to the M first PCIe interfaces.

Abstract: The present disclosure provides a data format conversion apparatus and method, and a buffer chip. The data format conversion apparatus is disposed on the buffer chip in a memory; a control module is disposed for sending a control instruction to a conversion module when obtaining a data copy command; and a conversion module is disposed for completing data format conversion and storage address mapping on to-be-converted data according to the received control instruction. In this way, a prior-art problem of additionally occupying computing resources and computation time of an accelerated computation unit due to a data format conversion unit disposed in the accelerated computation unit is avoided, the amount of data transmission between a main memory and a device memory is reduced without additionally occupying computing resources, and the computation precision is ensured while the computation efficiency is improved.