Patents by Inventor Liangbiao Chen
Liangbiao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136247Abstract: In at least one aspect, a method can include shaping a block of flexible spacer material. The method can include shaping a portion of the block of flexible spacer material to receive a solid metal block. The method can include coupling the solid metal block to the portion of the block of flexible spacer material.Type: ApplicationFiled: December 11, 2023Publication date: April 25, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Liangbiao CHEN, Yong LIU, Tzu-Hsuan CHENG, Stephen ST. GERMAIN, Roger ARBUTHNOT
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Publication number: 20240096734Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tzu-Hsuan CHENG, Yong LIU, Liangbiao CHEN
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Patent number: 11842942Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.Type: GrantFiled: March 18, 2022Date of Patent: December 12, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Liangbiao Chen, Yong Liu, Tzu-Hsuan Cheng, Stephen St. Germain, Roger Arbuthnot
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Patent number: 11830784Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.Type: GrantFiled: September 7, 2021Date of Patent: November 28, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tzu-Hsuan Cheng, Yong Liu, Liangbiao Chen
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Patent number: 11562938Abstract: A method includes bonding a device die to a direct bonded metal (DBM) substrate, bonding a spacer block to the device die, and at least partially reducing coefficient of thermal expansion (CTE) mismatches between the DBM substrate, the spacer block and the device die. At least partially reducing the CTE mismatches between the DBM substrate, the spacer block and the device die includes at least one of: disposing an arrangement of pillars and grooves in a surface region of the spacer block coupled to the device die, disposing at least one cavity in the spacer block, and disposing a groove in an outer conductive layer of the DBM substrate.Type: GrantFiled: December 29, 2020Date of Patent: January 24, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yong Liu, Liangbiao Chen, Yusheng Lin, Chee Hiong Chew
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Publication number: 20220208635Abstract: A method includes bonding a device die to a direct bonded metal (DBM) substrate, bonding a spacer block to the device die, and at least partially reducing coefficient of thermal expansion (CTE) mismatches between the DBM substrate, the spacer block and the device die. At least partially reducing the CTE mismatches between the DBM substrate, the spacer block and the device die includes at least one of: disposing an arrangement of pillars and grooves in a surface region of the spacer block coupled to the device die, disposing at least one cavity in the spacer block, and disposing a groove in an outer conductive layer of the DBM substrate.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yong LIU, Liangbiao CHEN, Yusheng LIN, Chee Hiong CHEW
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Publication number: 20220208637Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block. Claims 3 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.Type: ApplicationFiled: March 18, 2022Publication date: June 30, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Liangbiao CHEN, Yong LIU, Tzu-Hsuan CHENG, Stephen ST. GERMAIN, Roger ARBUTHNOT
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Patent number: 11282764Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.Type: GrantFiled: February 7, 2020Date of Patent: March 22, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Liangbiao Chen, Yong Liu, Tzu-Hsuan Cheng, Stephen St. Germain, Roger Arbuthnot
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Publication number: 20210398874Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.Type: ApplicationFiled: September 7, 2021Publication date: December 23, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tzu-Hsuan CHENG, Yong LIU, Liangbiao CHEN
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Publication number: 20210320013Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.Type: ApplicationFiled: June 25, 2021Publication date: October 14, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yong LIU, Yusheng LIN, Liangbiao CHEN
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Patent number: 11121055Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.Type: GrantFiled: January 10, 2020Date of Patent: September 14, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tzu-Hsuan Cheng, Yong Liu, Liangbiao Chen
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Publication number: 20210249329Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.Type: ApplicationFiled: February 7, 2020Publication date: August 12, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Liangbiao CHEN, Yong LIU, Tzu-Hsuan CHENG, Stephen ST. GERMAIN, Roger ARBUTHNOT
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Patent number: 11075090Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.Type: GrantFiled: November 5, 2019Date of Patent: July 27, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yong Liu, Yusheng Lin, Liangbiao Chen
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Publication number: 20210217679Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.Type: ApplicationFiled: January 10, 2020Publication date: July 15, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tzu-Hsuan CHENG, Yong LIU, Liangbiao CHEN
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Publication number: 20210134606Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.Type: ApplicationFiled: November 5, 2019Publication date: May 6, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yong LIU, Yusheng LIN, Liangbiao CHEN
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Publication number: 20110224101Abstract: Methods are provided for classification of cancer based on analysis of serologic biomarkers.Type: ApplicationFiled: November 9, 2010Publication date: September 15, 2011Inventors: Xuefeng Ling, James Schilling, Liangbiao Chen, Jiagang Zhao