Abstract: The invention provides a TFT backplane and manufacturing method thereof, wherein the TFT backplane comprises a substrate (1); a gate (11) and a first metal electrode (21) formed on the substrate (1); a gate insulating layer (31) formed on the substrate (1) and covering the gate (11) and the first metal electrode (21), the gate insulating layer (31) on the first metal electrode (21) having a thickness less than thickness of the gate insulating layer (32) on the gate (11); an etch stop layer (ESL) (5) on the gate insulating layer (31) and a second metal electrode (22) on the ESL (5). Only a portion of the gate insulating layer deposited on the first metal electrode is etched away, and the first metal electrode always protects the gate insulating layer, so that the first metal electrode is not damaged by the etching gas, favorable for the final storage capacitor.

Abstract: The present disclosure provides a display panel and a manufacturing process of the display panel. The manufacturing process of the display panel includes: successively depositing a plurality of thin-film layers on an auxiliary electrode layer, the compactness of a single thin-film layer among the plurality of thin-film layers gradually increasing from bottom to top; forming a preset pattern by the plurality of thin-film layers having a same width; dry-etching the plurality of thin-film layers so that the width of a single thin-film layer among the plurality of thin-film layers gradually increases from bottom to top, to form a plurality of cathode separators having an inverted trapezoid shape. The manufacturing process of the cathode separator is highly stable.

Abstract: A display panel is provided, which includes a substrate; a thin film transistor disposed on the substrate; a flat layer disposed on the thin film transistor; an anode disposed on the flat layer and penetrating the flat layer to be connected to the thin film transistor; a pixel definition layer disposed on the flat layer; a light shading layer disposed on the pixel definition layer, the light shading layer and the pixel definition layer having a pixel definition aperture exposing the anode; an OLED functional layer disposed on the exposed anode; a cathode disposed on the light shading layer and the OLED functional layer. The problem of light leakage of the pixel in the prior art can be eliminated and the display effect of the display panel can be improved.

Abstract: The present disclosure discloses an OLED display panel, including: a first substrate, a planarization layer, an auxiliary electrode, an anode formed on the planarization layer, a pixel definition layer, a cathode isolation column, an organic light-emitting layer, a cathode formed on the organic light-emitting layer. The cathode including a light-emitting cathode and an isolation cathode, the light-emitting cathode being disposed on the pixel definition layer and the pixel region, the isolation cathode being disposed on the cathode isolation column, the light-emitting cathode and the isolation cathode being isolated from each other by the cathode isolation column. An electrode stage electrically connected directly or indirectly to the auxiliary electrode, the cathode isolation column being formed on the electrode stage, the electrode stage electrically connected to the light-emitting cathode for the light-emitting cathode to receive a voltage on the auxiliary electrode.

Abstract: A polysilicon thin film transistor (TFT) structure includes a substrate, a buffer layer covering the substrate, an island shaped semiconductor layer positioned on the buffer layer, a gate isolation layer covering the island shaped semiconductor layer, a gate positioned on the gate isolation layer, a passivation layer positioned on the gate and the gate isolation layer, and a source and a drain positioned on the passivation layer. The island shaped semiconductor layer is formed with a process that includes forming a polysilicon thin film on the substrate and implementing silicon self-ion implantation to the polysilicon thin film with a dosage and an energy level that prevent the polysilicon thin film from being decrystallized. The silicon self-ion implanted polysilicon thin film is further subjected to photolithography and ion doping to form the island shaped semiconductor layer with ion doping areas.

Abstract: The disclosure provides a hybrid CMOS device and a manufacturing method thereof. The manufacturing method of the hybrid CMOS device according to the disclosure uses a low-temperature polysilicon to prepare an active layer of a PMOS transistor, and simultaneously uses a metal oxide semiconductor to prepare an active layer of an NMOS transistor. The two types of semiconductor materials are used in combination to form a hybrid CMOS device. Compared with the existing method for producing an active layer of the PMOS transistor by using a two-dimensional carbon nanotransister material or an organic semiconductor material, the hybrid CMOS device obtained according to the disclosure has superior electrical properties.

Abstract: The present disclosure provides a display panel and a manufacturing process of the display panel. The manufacturing process of the display panel includes: successively depositing a plurality of thin-film layers on an auxiliary electrode layer, the compactness of a single thin-film layer among the plurality of thin-film layers gradually increasing from bottom to top; forming a preset pattern by the plurality of thin-film layers having a same width; dry-etching the plurality of thin-film layers so that the width of a single thin-film layer among the plurality of thin-film layers gradually increases from bottom to top, to form a plurality of cathode separators having an inverted trapezoid shape. The manufacturing process of the cathode separator is highly stable.

Abstract: The present invention provides a manufacture method of a polysilicon thin film and a polysilicon TFT structure. The manufacture method of the polysilicon thin film comprises: step 1, providing a substrate (1), and forming the polysilicon thin film (3) on the substrate (1), and a thickness of the polysilicon thin film (3) accords with a required thickness of manufacturing a semiconductor element; step 2, implementing silicon self-ion implantation to the polysilicon thin film (3), and an implantation volume of silicon ion is lower than a measurement limit for making polysilicon be decrystallized. The manufacture method of the polysilicon thin film makes the implanted silicon ion to form interstitial silicon to move to the polysilicon grain boundary, which can reduce the defect concentration of the polysilicon grain boundary and improve the quality of the polysilicon thin film.

Abstract: A metal oxide thin film transistor includes: a substrate; a metal oxide semiconductor layer disposed on the substrate, and including a semiconductor body layer, and a source electrode contact layer and a drain electrode contact layer located at both ends of the semiconductor body layer, respectively; a gate insulating layer disposed on the semiconductor body layer; a gate electrode disposed on the gate insulating layer; a first passivation layer disposed on the gate electrode, the source electrode contact layer and the drain electrode contact layer, and having a first via hole and a second via hole exposing the source electrode contact layer and the drain electrode contact layer respectively; and a source electrode and a drain electrode disposed on the first passivation layer, the source electrode and the drain electrode contacting the source electrode contact layer and the drain electrode contact layer through the first and second via hole, respectively.

Abstract: The present invention provides a method for manufacturing an LTPS TFT substrate structure and a structure of an LTPS TFT substrate. The method for manufacturing the LTPS TFT substrate structure according to the present invention provides patterns of a thermally conductive electrical-insulation layer that are of the same size and regularly distributed under a buffer layer of a driving TFT area to absorb heat in a subsequent excimer laser annealing process so as to speed up the cooling rate of amorphous silicon to form crystal nuclei that gradually grow up in the annealing process. Since the thermally conductive electrical-insulation layer is made up of regularly distributed and size-consistent patterns, crystal grains of a polycrystalline silicon layer located in the driving TFT area show improved consistency and homogeneity and the grain sizes are relatively large to ensure the consistency of electrical property of the driving TFT.

Abstract: The present invention provides a manufacture method of a polysilicon thin film and a polysilicon TFT structure. The manufacture method of the polysilicon thin film comprises: step 1, providing a substrate (1), and forming the polysilicon thin film (3) on the substrate (1), and a thickness of the polysilicon thin film (3) accords with a required thickness of manufacturing a semiconductor element; step 2, implementing silicon self-ion implantation to the polysilicon thin film (3), and an implantation volume of silicon ion is lower than a measurement limit for making polysilicon be decrystallized. The manufacture method of the polysilicon thin film makes the implanted silicon ion to form interstitial silicon to move to the polysilicon grain boundary, which can reduce the defect concentration of the polysilicon grain boundary and improve the quality of the polysilicon thin film.

Abstract: The present invention provides a method for manufacturing an LTPS TFT substrate structure and a structure of an LTPS TFT substrate. The method for manufacturing the LTPS TFT substrate structure according to the present invention provides patterns of a thermally conductive electrical-insulation layer that are of the same size and regularly distributed under a buffer layer of a driving TFT area to absorb heat in a subsequent excimer laser annealing process so as to speed up the cooling rate of amorphous silicon to form crystal nuclei that gradually grow up in the annealing process. Since the thermally conductive electrical-insulation layer is made up of regularly distributed and size-consistent patterns, crystal grains of a polycrystalline silicon layer located in the driving TFT area show improved consistency and homogeneity and the grain sizes are relatively large to ensure the consistency of electrical property of the driving TFT.