Abstract: A system and a method for managing a memory, and an electronic device are provided. The system comprises a memory allocator and a trusted driving module. The memory allocator receives a first memory access request for a target partition of the memory and obtains authentication information to generate an authentication request. The memory allocator manages one or more physical memory partitions of the memory, and the target partition is one of the physical memory partitions. The trusted driving module is configured to receive the authentication request, generate an authentication result, and return the authentication result to the memory allocator. The memory allocator is further configured to execute the first memory access request when the authentication result indicates that the authentication succeeds, and reject the first memory access request when the authentication result indicates that the authentication fails. The system of the present disclosure enhances the security of memory operating.

Abstract: In a method and a system for accessing registers of a device, the device is connected to a CPU via a bus and includes multiple registers, each corresponding to a different address. Each register includes one or more storage units which share a register address. The access method includes: creating an instruction set for accessing the device; in response to operation requests from the CPU to the device, selecting corresponding instructions from the instruction set, to generate execution units with the minimum execution granularity corresponding to the operation requests; detecting the execution units, and when detecting that there are multiple execution units corresponding to the same type of operation request and multiple execution units includes multiple instructions of the same type corresponding to the same register address, merging and optimizing the multiple execution units to generate optimized execution units, and sending the optimized execution units to the bus.

Abstract: The present disclosure provides a method and apparatus for parsing contiguous system addresses, and an electronic device. The method for parsing contiguous system addresses comprises: acquiring system level information upon receiving contiguous system addresses; acquiring logical address ranges of objects in a first level based on the contiguous system addresses and the system level information; and when successively acquiring logical address ranges of objects in a second level, . . . , or an Nth level of the system, acquiring logical address ranges of objects in a present level based on a logical address range of a previous level and the system level information, wherein N is the number of levels, and N is an integer greater than or equal to 2, and a logical address range of an object comprises a start address and an end address of the object.

Abstract: The present disclosure provides a method and apparatus for parsing contiguous system addresses, and an electronic device. The method for parsing contiguous system addresses comprises: acquiring system level information upon receiving contiguous system addresses; acquiring logical address ranges of objects in a first level based on the contiguous system addresses and the system level information; and when successively acquiring logical address ranges of objects in a second level, . . . , or an Nth level of the system, acquiring logical address ranges of objects in a present level based on a logical address range of a previous level and the system level information, wherein N is the number of levels, and N is an integer greater than or equal to 2, and a logical address range of an object comprises a start address and an end address of the object.