Patents by Inventor Liangliang PING

Liangliang PING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for manufacturing laterally insulated-gate bipolar transistor
    Patent number: 9865702
    Abstract: The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 9, 2018
    Assignee: CSMC Technologies Fab2 Co., Ltd.
    Inventors: Feng Huang, Guangtao Han, Guipeng Sun, Feng Lin, Longjie Zhao, Huatang Lin, Bing Zhao, Lixiang Liu, Liangliang Ping, Fengying Chen
  • METHOD FOR MANUFACTURING LATERALLY INSULATED-GATE BIPOLAR TRANSISTOR
    Publication number: 20170358657
    Abstract: The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching
    Type: Application
    Filed: September 28, 2015
    Publication date: December 14, 2017
    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Feng HUANG, Guangtao HAN, Guipeng SUN, Feng LIN, Longjie ZHAO, Huatang LIN, Bing ZHAO, Lixiang LIU, Liangliang PING, Fengying CHEN