Patents by Inventor Liangwei Mou

Liangwei Mou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method for manufacturing same
    Patent number: 9548297
    Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a PIP capacitor located. The PIP capacitor includes a first polysilicon layer, a metallic silicide layer, a protective layer, a dielectric layer, and a second polysilicon layer, which have a lower conductive plate pattern and are successively arranged. The method includes: providing a substrate; successively forming a first polysilicon layer, a metallic silicide, and a protective layer on the substrate; transferring a lower conductive plate pattern into the first polysilicon layer, the metallic silicide layer, and the protective layer, thus forming the first polysilicon layer, the metallic silicide layer, and the protective layer having the lower conductive plate pattern; successively forming a dielectric layer and a second polysilicon layer having a lower conductive plate pattern on the protective layer. The capacitance and reliability of the PIP capacitor are improved.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: January 17, 2017
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Liangwei Mou, Zhaoxing Huang, Xuelei Chen, Li Wang, Zhewei Wang
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    Publication number: 20140167126
    Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a PIP capacitor located. The PIP capacitor includes a first polysilicon layer, a metallic silicide layer, a protective layer, a dielectric layer, and a second polysilicon layer, which have a lower conductive plate pattern and are successively arranged. The method includes: providing a substrate; successively forming a first polysilicon layer, a metallic silicide, and a protective layer on the substrate; transferring a lower conductive plate pattern into the first polysilicon layer, the metallic silicide layer, and the protective layer, thus forming the first polysilicon layer, the metallic silicide layer, and the protective layer having the lower conductive plate pattern; successively forming a dielectric layer and a second polysilicon layer having a lower conductive plate pattern on the protective layer. The capacitance and reliability of the PIP capacitor are improved.
    Type: Application
    Filed: July 31, 2012
    Publication date: June 19, 2014
    Applicant: CSMC Technologies FAB2 Co., Ltd
    Inventors: Liangwei Mou, Zhaoxing Huang, Xuelei Chen, Li Wang, Zhewei Wang