Abstract: The present invention discloses a radiation-hardened-by-design (RHBD) multi-gate device and a fabrication method thereof. The multi-gate device of the present invention includes a substrate; a source region and a drain region, which are on the substrate; a protruding fin structure and a field dielectric layer between the source region and the drain region on the substrate; a gate dielectric and a gate electrode on the fin structure and the dielectric layer; and two isolation layers separated to each other, which are disposed in the drain region between the adjacent two fins, wherein an interlayer is sandwiched between the two isolation layers.

Abstract: The present invention discloses a radiation-hardened-by-design (RHBD) multi-gate device and a fabrication method thereof. The multi-gate device of the present invention includes a substrate; a source region and a drain region, which are on the substrate; a protruding fin structure and a field dielectric layer between the source region and the drain region on the substrate; a gate dielectric and a gate electrode on the fin structure and the dielectric layer; and two isolation layers separated to each other, which are disposed in the drain region between the adjacent two fins, wherein an interlayer is sandwiched between the two isolation layers.

Abstract: The present invention discloses a method for separating SOI device threshold voltage shift under a DC HCl stress, which belongs to a semiconductor reliability test field. By means of this method, under the condition that stressing bias is applied simultaneously to a gate terminal and a drain terminal of the SOI PMOSFET, the influences of HCl effect and NBTI effect are separated on the threshold voltage shift under the DC HCl stress. Adopting the present invention helps to better understand degradation mechanisms from HCl effect under stress with VG=VD, so as to better build model for the device and more accurately predict the device lifetime.

Abstract: A radiation resistant CMOS device and a method for fabricating the same. The CMOS device includes a substrate, a source region, a drain region and a vertical channel on the substrate. A first dielectric protection region is inserted into the vertical channel at the center of the vertical channel to divide the vertical channel into two parts and has a height equal to the length of the vertical channel. The edge of the first dielectric protection region is 20-100 nm from an outer side of the channel, with a central axis of an silicon platform for an active region as the center. A second dielectric protection region is disposed under the source or drain region, with a length equal to the length of the source or drain region and a height of 10-50 nm. The dielectric protection regions effectively block paths for the source and drain regions collecting charges.