Abstract: A capacitor structure includes two electrodes arranged oppositely and a dielectric layer located between the two electrodes, wherein the dielectric layer includes at least two perovskite layers stacked; an amorphous layer is provided between every two adjacent perovskite layers; two outermost perovskite layers of the at least two perovskite layers are in contact with the two electrodes, respectively.

Abstract: Embodiment relates to the field of semiconductor technologies, and proposes a semiconductor device and a fabrication method thereof. The semiconductor device includes: a substrate, a semiconductor structure, an insulating layer, and a conductive layer. The semiconductor structure is positioned on a side of the substrate and includes a first semiconductor structure and a second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure form a PN junction. The insulating layer is positioned on a side of the semiconductor structure facing away from the substrate. The conductive layer is positioned on a side of the insulating layer facing away from the substrate, and an orthographic projection of the conductive layer on the substrate at least partially overlaps an orthographic projection of the PN junction on the substrate.

Abstract: A garment, particularly a garment useful in a medical setting, comprising a gown that provides an acceptable barrier between a wearer and certain contaminants as well as easy doffing, the gown having a neck opening, two sleeves, a body portion including a front body portion and a back body portion, one or more panels, and/or one or more doffing features.

Abstract: A garment, particularly a garment useful in a medical setting, comprising a gown that provides an acceptable barrier between a wearer and certain contaminants as well as easy doffing, the gown having a neck opening, two sleeves, a body portion including a front body portion and a back body portion, one or more panels, and/or one or more doffing features.

Abstract: A method for forming a semiconductor structure includes: providing a substrate, grooves having a first depth being provided; forming a first gate oxide layer on side walls and a bottom surface of a groove, and a first gate conductive layer on a surface of the first gate oxide layer, the first gate oxide layer and the first gate conductive layer having a second depth which is less than the first depth; forming a second gate oxide layer on surfaces of the groove that are not covered by the first gate oxide layer, in a direction perpendicular to a side wall of the groove, an equivalent gate oxide thickness of the second gate oxide layer being greater than that of the first gate oxide layer; and forming a second gate conductive layer which fills up a recess surrounded by the second gate oxide layer and the first gate conductive layer.

Abstract: A preparation method for the capacitor structure includes: forming a dielectric layer on a first electrode, wherein, the dielectric layer includes a first amorphous layer and a high dielectric constant layer which are stacked, the first amorphous layer maintaining an amorphous structure after annealing, and the high dielectric constant layer being formed by crystallizing an initial dielectric constant layer after annealing; and forming a second electrode on the dielectric layer. Since the first amorphous layer remains an amorphous structure after annealing, electron transport can be suppressed, thereby reducing the leakage current of the capacitor structure.

Abstract: Embodiment relates to the field of semiconductor technologies, and proposes a semiconductor device and a fabrication method thereof. The semiconductor device includes: a substrate, a semiconductor structure, an insulating layer, and a conductive layer. The semiconductor structure is positioned on a side of the substrate and includes a first semiconductor structure and a second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure form a PN junction. The insulating layer is positioned on a side of the semiconductor structure facing away from the substrate. The conductive layer is positioned on a side of the insulating layer facing away from the substrate, and an orthographic projection of the conductive layer on the substrate at least partially overlaps an orthographic projection of the PN junction on the substrate.