Patents by Inventor Lian-Jie LI

Lian-Jie LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240250170
    Abstract: A semiconductor device includes a gate structure, a drift region, a source region, a drain region, a first doped region, and a second doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The first doped region is in the drift region and between the drain region and the gate structure. The second doped region is within the drift region. The second doped region forms a P-N junction with the first doped region at a bottom surface of the first doped region.
    Type: Application
    Filed: April 3, 2024
    Publication date: July 25, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC China Company Limited
    Inventors: Lian-Jie LI, Yan-Bin LU, Feng HAN, Shuai ZHANG
  • Patent number: 12040358
    Abstract: A super junction structure includes a substrate, wherein the substrate has a first conductivity type. The super junction structure includes an epitaxial layer over the substrate, wherein the epitaxial layer has a second conductivity type opposite the first conductivity type. The super junction structure further includes a bury layer between the epitaxial layer and the substrate, wherein the bury layer has the second conductivity type. The super junction structure further includes a conductive pillar in the epitaxial layer, wherein the conductive pillar has the first conductivity type, sidewalls of the conductive pillar are angled with respect to a top-most surface of the epitaxial layer, a bottom surface of the conductive pillar is rounded, and a top-most surface of the conductive pillar is coplanar with the top-most surface of the epitaxial layer.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuai Zhang, Feng Han, Jian Wu, Lian-Jie Li, Zhong-Hao Chen
  • Patent number: 11978797
    Abstract: A semiconductor device includes a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The doped region is in the drift region and between the drain region and the gate structure. From a top view the doped region has a strip pattern extending in parallel with a strip pattern of the gate structure.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 7, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Lian-Jie Li, Yan-Bin Lu, Feng Han, Shuai Zhang
  • Publication number: 20230387196
    Abstract: A super junction structure includes a substrate, wherein the substrate has a first conductivity type. The super junction structure includes an epitaxial layer over the substrate, wherein the epitaxial layer has a second conductivity type opposite the first conductivity type. The super junction structure further includes a bury layer between the epitaxial layer and the substrate, wherein the bury layer has the second conductivity type. The super junction structure further includes a conductive pillar in the epitaxial layer, wherein the conductive pillar has the first conductivity type, sidewalls of the conductive pillar are angled with respect to a top-most surface of the epitaxial layer, a bottom surface of the conductive pillar is rounded, and a top-most surface of the conductive pillar is coplanar with the top-most surface of the epitaxial layer.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Shuai ZHANG, Feng HAN, Jian WU, Lian-Jie LI, Zhong-Hao CHEN
  • Publication number: 20220384648
    Abstract: A semiconductor device includes a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The doped region is in the drift region and between the drain region and the gate structure. From a top view the doped region has a strip pattern extending in parallel with a strip pattern of the gate structure.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC China Company Limited
    Inventors: Lian-Jie LI, Yan-Bin LU, Feng HAN, Shuai ZHANG
  • Patent number: 11469322
    Abstract: A semiconductor device includes a substrate, a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is above the substrate. The drift region is in the substrate and under the gate structure. The source region and the drain region are on opposite sides of the gate structure. The drain region is in the drift region, and the source region is outside the drift region. The doped region is in the drift region and between the drain region and the gate structure. The doped region is spaced apart from a bottom surface of the drain region.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: October 11, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Lian-Jie Li, Yan-Bin Lu, Feng Han, Shuai Zhang
  • Publication number: 20220069074
    Abstract: A super junction structure includes a substrate, wherein the substrate has a first conductivity type. The super junction structure includes an epitaxial layer over the substrate, wherein the epitaxial layer has a second conductivity type opposite the first conductivity type. The super junction structure further includes a bury layer between the epitaxial layer and the substrate, wherein the bury layer has the second conductivity type. The super junction structure further includes a conductive pillar in the epitaxial layer, wherein the conductive pillar has the first conductivity type, sidewalls of the conductive pillar are angled with respect to a top-most surface of the epitaxial layer, a bottom surface of the conductive pillar is rounded, and a top-most surface of the conductive pillar is coplanar with the top-most surface of the epitaxial layer.
    Type: Application
    Filed: November 9, 2021
    Publication date: March 3, 2022
    Inventors: Shuai ZHANG, Feng HAN, Jian WU, Lian-Jie LI, Zhong-Hao CHEN
  • Patent number: 11201211
    Abstract: A method of manufacturing a super junction structure includes etching a material to define a trench, wherein the trench has a tapered profile. The method further includes implanting dopants into sidewalls and a bottom surface of the trench to define a doped region, wherein the doped region surrounds the trench. The method further includes depositing an undoped material into the trench. The method further includes performing a thermal process, wherein the thermal process drives the dopants from the doped region into the undoped material to form a conductive pillar in the trench.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuai Zhang, Lian-Jie Li, Zhong-Hao Chen, Feng Han, Jian Wu
  • Publication number: 20210367074
    Abstract: A semiconductor device includes a substrate, a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is above the substrate. The drift region is in the substrate and under the gate structure. The source region and the drain region are on opposite sides of the gate structure. The drain region is in the drift region, and the source region is outside the drift region. The doped region is in the drift region and between the drain region and the gate structure. The doped region is spaced apart from a bottom surface of the drain region.
    Type: Application
    Filed: July 16, 2020
    Publication date: November 25, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC China Company Limited
    Inventors: Lian-Jie LI, Yan-Bin LU, Feng HAN, Shuai ZHANG
  • Publication number: 20200251553
    Abstract: A method of manufacturing a super junction structure includes etching a material to define a trench, wherein the trench has a tapered profile. The method further includes implanting dopants into sidewalls and a bottom surface of the trench to define a doped region, wherein the doped region surrounds the trench. The method further includes depositing an undoped material into the trench. The method further includes performing a thermal process, wherein the thermal process drives the dopants from the doped region into the undoped material to form a conductive pillar in the trench.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Inventors: Shuai ZHANG, Lian-Jie LI, Zhong-Hao CHEN, Feng HAN, Jian WU
  • Publication number: 20160126307
    Abstract: A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a plurality of pillars of a second conductivity type, a plurality of gate trenches, an insulating layer and a plurality of doped wells of the second conductivity type. The epitaxial layer of the first conductivity type is on the substrate. The pillars of the second conductivity type are in the epitaxial layer, in which the second conductivity type is opposite to the first conductivity type. The gate trenches are individually corresponding to and over the pillars. The insulating layer is in the gate trenches. The doped wells of the second conductivity type are in the epitaxial layer, in which each of the doped wells is between two adjacent gate trenches. A method for manufacturing the semiconductor device and a method for manufacturing a super junction structure are also provided.
    Type: Application
    Filed: December 30, 2014
    Publication date: May 5, 2016
    Inventors: Shuai ZHANG, Lian-Jie LI, Zhong-Hao CHEN, Feng HAN, Jian WU