Patents by Inventor Lianjuan Ren

Lianjuan Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11876016
    Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method for forming a hole structure having a first hole portion and a second hole portion connected to and over the first portion in a stack structure of a semiconductor device includes determining a hard mask layer. An etching resistivity of the hard mask layer may be inversely proportional to a difference between a first lateral dimension of the first hole portion and a second lateral dimension of the second hole portion, and the first lateral dimension may be less than the second lateral dimension. The method may also include forming the hard mask layer over the stack structure, and patterning the hard mask layer to form a first patterned hard mask layer that has a first mask opening. The first mask opening may have the first lateral dimension.
    Type: Grant
    Filed: November 21, 2020
    Date of Patent: January 16, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Gang Yang, Xiang Hui Zhao, Biao Zheng, Zui Xin Zeng, Lianjuan Ren, Jian Dai
  • Patent number: 11817348
    Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method includes forming a first etch mask over a stack structure, and removing a portion of the stack structure exposed by the first etch mask. The first etch mask may have a first mask opening with a first lateral dimension. The method may also include forming a second etch mask from the first etch mask. The second etch mask may have a second mask opening with a second lateral dimension that is greater than the first lateral dimension. The method may further include removing another portion of the stack structure exposed by the second etch mask to form the hole structure having a first hole portion and a second hole portion connected to and over the first hole portion.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 14, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Gang Yang, Xiang Hui Zhao, Biao Zheng, Zui Xin Zeng, Lianjuan Ren, Jian Dai
  • Patent number: 11631592
    Abstract: In a method, a mask is formed on a microstructure over a substrate. The mask includes a first pattern over a first region of the microstructure and a second pattern over a second region of the microstructure. A first etching process is performed to etch the microstructure by providing an etching gas and applying a first bias voltage to the substrate according to the first and second patterns of the mask. A protective layer is subsequently formed by providing a deposition gas and applying a second bias voltage to the substrate to cover the first pattern of the mask. A second etching process is performed to transfer the second pattern of the mask further into the second region of the microstructure. The deposition gas has a higher carbon to fluorine ratio than the etching gas, and the second bias voltage is smaller than the first bias voltage.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: April 18, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yu Qi Wang, Wenjie Zhang, Hong Guang Song, Lipeng Liu, Lianjuan Ren
  • Publication number: 20210287914
    Abstract: In a method, a mask is formed on a microstructure over a substrate. The mask includes a first pattern over a first region of the microstructure and a second pattern over a second region of the microstructure. A first etching process is performed to etch the microstructure by providing an etching gas and applying a first bias voltage to the substrate according to the first and second patterns of the mask. A protective layer is subsequently formed by providing a deposition gas and applying a second bias voltage to the substrate to cover the first pattern of the mask. A second etching process is performed to transfer the second pattern of the mask further into the second region of the microstructure. The deposition gas has a higher carbon to fluorine ratio than the etching gas, and the second bias voltage is smaller than the first bias voltage.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yu Qi WANG, Wenjie ZHANG, Hong Guang SONG, Lipeng LIU, Lianjuan REN
  • Patent number: 11062913
    Abstract: In the disclosed method, a mask is formed on a microstructure. The mask includes a first pattern positioned over a first region of the microstructure and a second pattern positioned over a second region of the microstructure. A first etching process is performed to etch the microstructure according to the first and second patterns formed in the mask. The first etching process transfers the first and second patterns of the mask into the first and second regions of the microstructure, respectively. A protective layer is subsequently formed over the first pattern of the mask that is positioned over the first region of the microstructure. When the protective layer is formed, a second etching process is performed to etch the microstructure and transfer the second pattern of the mask further into the second region of the microstructure. The method also includes removing the mask and the protective layer from the microstructure.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: July 13, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yu Qi Wang, Wenjie Zhang, Hong Guang Song, Lipeng Liu, Lianjuan Ren
  • Publication number: 20210104429
    Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method for forming a hole structure having a first hole portion and a second hole portion connected to and over the first portion in a stack structure of a semiconductor device includes determining a hard mask layer. An etching resistivity of the hard mask layer may be inversely proportional to a difference between a first lateral dimension of the first hole portion and a second lateral dimension of the second hole portion, and the first lateral dimension may be less than the second lateral dimension. The method may also include forming the hard mask layer over the stack structure, and patterning the hard mask layer to form a first patterned hard mask layer that has a first mask opening. The first mask opening may have the first lateral dimension.
    Type: Application
    Filed: November 21, 2020
    Publication date: April 8, 2021
    Inventors: Gang Yang, Xiang Hui Zhao, Biao Zheng, Zui Xin Zeng, Lianjuan Ren, Jian Dai
  • Publication number: 20200258757
    Abstract: In the disclosed method, a mask is formed on a microstructure. The mask includes a first pattern positioned over a first region of the microstructure and a second pattern positioned over a second region of the microstructure. A first etching process is performed to etch the microstructure according to the first and second patterns formed in the mask. The first etching process transfers the first and second patterns of the mask into the first and second regions of the microstructure, respectively. A protective layer is subsequently formed over the first pattern of the mask that is positioned over the first region of the microstructure. When the protective layer is formed, a second etching process is performed to etch the microstructure and transfer the second pattern of the mask further into the second region of the microstructure. The method also includes removing the mask and the protective layer from the microstructure.
    Type: Application
    Filed: March 27, 2019
    Publication date: August 13, 2020
    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yu Qi WANG, Wenjie ZHANG, Hong Guang SONG, Lipeng LIU, Lianjuan REN
  • Publication number: 20200243373
    Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method includes forming a first etch mask over a stack structure, and removing a portion of the stack structure exposed by the first etch mask. The first etch mask may have a first mask opening with a first lateral dimension. The method may also include forming a second etch mask from the first etch mask. The second etch mask may have a second mask opening with a second lateral dimension that is greater than the first lateral dimension. The method may further include removing another portion of the stack structure exposed by the second etch mask to form the hole structure having a first hole portion and a second hole portion connected to and over the first hole portion.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 30, 2020
    Inventors: Gang Yang, Xiang Hui Zhao, Biao Zheng, Zui Xin Zeng, Lianjuan Ren, Jian Dai