Abstract: A circuit and a method for removing spread spectrum are provided. The circuit includes a data clock recovery module and a clock extraction module that are connected. The data clock recovery module performs clock recovery on an input signal carrying spread spectrum information to obtain a parallel clock signal and a first signal, where the parallel clock signal includes frequency information and phase information, and the first signal includes the frequency information. The clock extraction module divides a frequency of the parallel clock signal to obtain a reference clock signal; acquires a feedback clock signal based on the first signal; acquires a de-spread clock signal based on the reference clock signal and the feedback clock signal, where the de-spread clock signal includes the phase information and does not include the frequency information; and divides a frequency of the de-spread clock signal to obtain an output clock signal.

Abstract: A method and a system for automatically adjusting intensity of a signal outputted by an HDMI transmitter are provided. With the method, a length of an HDMI transmission line between the HDMI transmitter and an HDMI receiver is determined. A swing amplitude and a pre-emphasis intensity of the signal outputted by the HDMI transmitter are determined based on the length of the HDMI transmission line and a frequency of the signal outputted by the HDMI transmitter. An HDMI output drive circuit is configured based on the swing amplitude and the pre-emphasis intensity.

Abstract: A method and a system for automatically adjusting intensity of a signal outputted by an HDMI transmitter are provided. With the method, a length of an HDMI transmission line between the HDMI transmitter and an HDMI receiver is determined. A swing amplitude and a pre-emphasis intensity of the signal outputted by the HDMI transmitter are determined based on the length of the HDMI transmission line and a frequency of the signal outputted by the HDMI transmitter. An HDMI output drive circuit is configured based on the swing amplitude and the pre-emphasis intensity.

Abstract: A conversion apparatus, a storage device and a method for manufacturing the same are provided. The storage device may include a DDR storage layer, a DDR interface layer, a conversion logic circuit layer, and a peripheral interface layer. The peripheral interface layer may include a GDDR interface layer or a PCIe interface layer. The conversion logic circuit layer may process, by using DDR storage logic, data obtained through the peripheral interface layer and transfer processed data to the DDR interface layer, or process, by using GDDR storage logic, data obtained through the DDR interface layer and transfer processed data to the peripheral interface Layer. The DDR storage layer may be connected to the DDR interface layer, so that the conversion logic circuit layer can convert the storage logic of the data from DDR to GDDR or from GDDR to DDR.

Abstract: A conversion apparatus, a storage device and a method for manufacturing the same are provided. The storage device may include a DDR storage layer, a DDR interface layer, a conversion logic circuit layer, and a peripheral interface layer. The peripheral interface layer may include a GDDR interface layer or a PCIe interface layer. The conversion logic circuit layer may process, by using DDR storage logic, data obtained through the peripheral interface layer and transfer processed data to the DDR interface layer, or process, by using GDDR storage logic, data obtained through the DDR interface layer and transfer processed data to the peripheral interface Layer. The DDR storage layer may be connected to the DDR interface layer, so that the conversion logic circuit layer can convert the storage logic of the data from DDR to GDDR or from GDDR to DDR.

Abstract: A clock and data recovery circuit and a phase interpolator therefor are provided. The clock and data recovery circuit includes a phase-locked loop, a control unit and the phase interpolator, a receiving circuit, a serial-to-parallel conversion circuit. The phase interpolator is connected with the control unit of the clock and data recovery circuit, and the phase interpolator includes: an encoding circuit, two multiplexers, a clock mixer, and two differential to single-ended amplifiers. The control unit is configured to further control the encoding circuit to change a delay position for a clock outputted by the phase interpolator in a case that the data sampled in the current clock position is not the optimal sampled data, to lead or lag the clock, thereby forming a stable state in which the clock follows the data dynamically.

Abstract: A clock and data recovery circuit and a phase interpolator therefor are provided. The clock and data recovery circuit includes a phase-locked loop, a control unit and the phase interpolator, a receiving circuit, a serial-to-parallel conversion circuit. The phase interpolator is connected with the control unit of the clock and data recovery circuit, and the phase interpolator includes: an encoding circuit, two multiplexers, a clock mixer, and two differential to single-ended amplifiers. The control unit is configured to further control the encoding circuit to change a delay position for a clock outputted by the phase interpolator in a case that the data sampled in the current clock position is not the optimal sampled data, to lead or lag the clock, thereby forming a stable state in which the clock follows the data dynamically.

Abstract: A signal transmission method for a USB interface and an apparatus thereof are provided. The method includes: receiving a first USB signal sent from a sending terminal, processing the first USB signal into a USB-like signal, and transmitting the USB-like signal via a networking cable; receiving the USB-like signal, processing the USB-like signal into a second USB signal, and sending the second USB signal to a receiving terminal. According to the embodiments of the present invention, the first USB signal is processed into a USB-like signal which is similar to the USB signal, the USB-like signal is transmitted via a networking cable, and the USB-like signal is processed into a second USB signal. The transmission process does not require converting the USB signal into a networking-cable signal which is to be transmitted via a networking cable, thereby avoiding conversion between protocols, and simplifying the entire transmission process.

Abstract: The present invention provides a clock and data recovery circuit, including an n-phase clock, a sampling and edge detection unit, an edge determination unit, a clock picking unit and a data picking unit. The sampling and edge detection unit performs spaced sampling on the input serial data using the n-phase clock, and performs edge detection and resampling on the sampled data. The edge determination unit filters the resampled data by the counting units, and obtains the positions of the edges of the serial data according to the counting result of the counting units. The clock picking unit selects a clock from the n clocks that is the farthest away from the edges as the recovered clock. The data picking unit obtains the recovered data according to the recovered clock. The present invention also provides a parallel output circuit.

Abstract: A signal transmission method for a USB interface and an apparatus thereof are provided. The method includes: receiving a first USB signal sent from a sending terminal, processing the first USB signal into a USB-like signal, and transmitting the USB-like signal via a networking cable; receiving the USB-like signal, processing the USB-like signal into a second USB signal, and sending the second USB signal to a receiving terminal. According to the embodiments of the present invention, the first USB signal is processed into a USB-like signal which is similar to the USB signal, the USB-like signal is transmitted via a networking cable, and the USB-like signal is processed into a second USB signal. The transmission process does not require converting the USB signal into a networking-cable signal which is to be transmitted via a networking cable, thereby avoiding conversion between protocols, and simplifying the entire transmission process.

Abstract: The present invention provides a clock and data recovery circuit, including an n-phase clock, a sampling and edge detection unit, an edge determination unit, a clock picking unit and a data picking unit. The sampling and edge detection unit performs spaced sampling on the input serial data using the n-phase clock, and performs edge detection and resampling on the sampled data. The edge determination unit filters the resampled data by the counting units, and obtains the positions of the edges of the serial data according to the counting result of the counting units. The clock picking unit selects a clock from the n clocks that is the farthest away from the edges as the recovered clock. The data picking unit obtains the recovered data according to the recovered clock. The present invention also provides a parallel output circuit.