Abstract: Testing packaged integrated circuit (IC) devices is difficult and time consuming. When multiple devices (dies) are packaged to produce a SiP (system in package) the devices should be tested for defects that may be introduced during the packaging process. With limited access to the inputs and outputs of the devices, test times increase compared with testing the devices before they are packaged. A CoWoS (chip on wafer on substrate) SiP includes a logic device and a memory device and has interfaces between the logic device and memory device that cannot be directly accessed at a package ball. Test programs are concurrently executed by the logic device and the memory device to reduce testing time. Each memory device includes a BIST (built-in self-test) module that is initialized and executes the memory test program while the one or more modules within the logic device are tested.

Abstract: Testing packaged integrated circuit (IC) devices is difficult and time consuming. When multiple devices (dies) are packaged to produce a SiP (system in package) the devices should be tested for defects that may be introduced during the packaging process. With limited access to the inputs and outputs of the devices, test times increase compared with testing the devices before they are packaged. A CoWoS (chip on wafer on substrate) SiP includes a logic device and a memory device and has interfaces between the logic device and memory device that cannot be directly accessed at a package ball. Test programs are concurrently executed by the logic device and the memory device to reduce testing time. Each memory device includes a BIST (built-in self-test) module that is initialized and executes the memory test program while the one or more modules within the logic device are tested.

Abstract: A system and method are disclosed for testing a settling time of a device-under-test (DUT). A method for determining a settling time of a device-under-test (DUT) includes activating a DUT to generate an output signal and mixing the output signal of the DUT and a reference signal to generate a mixed signal. An amplitude threshold is set for the mixed signal relative to an amplitude of the mixed signal and the settling time of the DUT is determined based on a last time that the amplitude of the mixed signal crosses the amplitude threshold relative to the activation of the DUT.

Abstract: In a method and system for testing a transceiver communication device operating in a test mode, a transmitter output signal generated by a transmitter is adjusted and provided as a loop back to a receiver. The adjustment includes shifting a frequency and attenuating amplitude of the transmitter output signal to substantially match a predefined frequency and a predefined amplitude of a receiver input signal received by the receiver. A pass or fail status of the device is determined by comparing transmitted and received data.

Abstract: According to one embodiment of the invention, a system for testing electronic devices includes a first RF source operable to output a first signal, a second RF source operable to output a second signal, a combiner coupled to the first and second RF sources and operable to combine the first and second signals to create a third signal, one or more down converters operable to receive respective output signals from respective electronic devices and create respective down converted signals, and a set of switches operable to switch the second RF source to a local oscillator function that couples to the one or more down converters for inputting respective reference signals into the one or more down converters.

Abstract: In a method and system for testing a transceiver communication device operating in a test mode, a transmitter output signal generated by a transmitter is adjusted and provided as a loop back to a receiver. The adjustment includes shifting a frequency and attenuating amplitude of the transmitter output signal to substantially match a predefined frequency and a predefined amplitude of a receiver input signal received by the receiver. A pass or fail status of the device is determined by comparing transmitted and received data.

Abstract: A system and method are disclosed for testing a settling time of a device-under-test (DUT). A method for determining a settling time of a device-under-test (DUT) includes activating a DUT to generate an output signal and mixing the output signal of the DUT and a reference signal to generate a mixed signal. An amplitude threshold is set for the mixed signal relative to an amplitude of the mixed signal and the settling time of the DUT is determined based on a last time that the amplitude of the mixed signal crosses the amplitude threshold relative to the activation of the DUT.

Abstract: According to one embodiment of the invention, a system for testing electronic devices includes a first RF source operable to output a first signal, a second RF source operable to output a second signal, a combiner coupled to the first and second RF sources and operable to combine the first and second signals to create a third signal, one or more down converters operable to receive respective output signals from respective electronic devices and create respective down converted signals, and a set of switches operable to switch the second RF source to a local oscillator function that couples to the one or more down converters for inputting respective reference signals into the one or more down converters.

Abstract: According to one embodiment of the invention, a method for testing a device is provided. The method includes testing an electronic device having a first operating frequency by a tester device having a second operating frequency. The method also includes determining, during the test, a frequency difference between the first operating frequency and the second operating frequency. The method also includes initiating an equalization of the first and the second operating frequencies using a signal indicative of the frequency difference.