Patents by Inventor Liav Ben Artsi

Liav Ben Artsi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11917749
    Abstract: An integrated circuit package, including a circuit board, signal pins extending orthogonally to the circuit board surface, and grouped into a plurality of differential signal pin pairs, each signal pin pair positioned at a vertex of an array of orthogonal rows and columns, wherein each signal pin pair includes a positive and a negative signal pin. The plurality of signal pin pairs includes a first subset of signal pin pairs wherein the positive and the negative signal pins are arranged in an orientation along a line parallel to rows of the array and a second subset of signal pin pairs in which the positive and the negative signal pins are arranged in an orientation along a line parallel to columns of the array. For each signal pin pair in one of the first and second subsets, each nearest signal pin pairs belong to another of the first and second subsets.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: February 27, 2024
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Dan Azeroual, Liav Ben Artsi
  • Publication number: 20240008180
    Abstract: A printed circuit board (PCB) includes a plurality of stacked layers, each layer having a major plane defining a major plane of the PCB, a plurality of signal pads disposed on a signal pad layer of the PCB that is parallel to the major plane of the PCB, and a plurality of signal vias, each signal via in the plurality of signal vias having a longitudinal axis perpendicular to the major plane of the PCB, each signal via extending through the plurality of layers along the longitudinal axis, each respective signal via being electrically coupled to a respective signal pad of the plurality of signal pads, wherein at least one signal via in the plurality of signal vias includes an added capacitive structure which, along with inductance of that via, forms a corrective filter to reduce insertion loss deviation of at least one broadband signal in that via.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 4, 2024
    Inventors: Liav Ben Artsi, Noam Kutscher
  • Patent number: 11789067
    Abstract: An integrated circuit (IC) is manufactured and is mounted in an IC package. A processor of a measurement system determines a reference value of a physical layer (PHY) parameter at a second test point on a test fixture based on one or more model values, specified by an Ethernet communication standard, corresponding to a first test point on the test fixture corresponding to a contact on the IC package and one or more measured test fixture parameters characterizing a channel connecting the first test point to the second test point on the test fixture. The processor then determines whether the PHY parameter at the first test point on the IC package complies with the Ethernet communication standard based on i) the reference value of the PHY parameter and ii) a measured value of the PHY parameter obtained from a measurement of the PHY parameter at the second test point.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: October 17, 2023
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Liav Ben Artsi
  • Publication number: 20230187423
    Abstract: A printed circuit board (PCB) system includes an integrated circuit (IC) package having a main IC chip that is electrically coupled to a top surface of a package substrate. A first printed circuit board (PCB) is electrically coupled to first contact structures on a bottom surface of the package substrate. A heat dissipation member is coupled to the main IC chip. A memory module is configured to electrically couple, via an interposer, with second contact structures on a top surface of the package substrate while the heat dissipation member dissipates heat from the main IC chip away from one or more memory IC chips on the memory module. The interposer is configured to electrically couple the second contact structures of the IC package with the memory module while the heat dissipation member dissipates heat from the main IC chip away from the one or more memory IC chips.
    Type: Application
    Filed: February 10, 2023
    Publication date: June 15, 2023
    Inventors: Dan AZEROUAL, Liav BEN ARTSI
  • Patent number: 11581292
    Abstract: A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: February 14, 2023
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Dan Azeroual, Liav Ben Artsi
  • Publication number: 20200388598
    Abstract: A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 10, 2020
    Inventors: Dan AZEROUAL, Liav BEN ARTSI
  • Patent number: 9921596
    Abstract: A power supply noise reduction circuit and a power supply noise reduction method are provided. An integrated circuit includes an input node configured to receive a signal via a transmission line. The integrated circuit also includes termination circuitry configured to electrically couple the input node to a power rail of the integrated circuit. The integrated circuit further includes a circuit component coupled to the power rail. The circuit component is configured to bleed off a portion of current on the power rail based on a determination that a voltage on the power rail meets or exceeds a high voltage threshold. The circuit component is also configured to bleed off a smaller portion of the current on the power rail based on a determination that the voltage on the power rail is less than the high voltage threshold.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: March 20, 2018
    Assignee: MARVELL ISRAEL (M.I.S.L) LTD
    Inventor: Liav Ben Artsi
  • Patent number: 9143368
    Abstract: Systems and methods are provided for an equalizer. An equalizer includes a first voltage correcting circuit configured to correct a communication signal by applying a first variable corrective voltage to the communication signal, the first corrective voltage having a voltage level selected according to a first adjustable granularity. A second voltage correcting circuit is configured to further correct the communication signal by applying a second variable corrective voltage to the communication signal, the second corrective voltage having a voltage level selected according to a second adjustable granularity that is different from the first adjustable granularity.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: September 22, 2015
    Assignee: MARVELL ISRAEL (M.I.S.L.) LTD.
    Inventors: Liav Ben Artsi, Miki Moyal
  • Patent number: 9124461
    Abstract: Aspects of the disclosure provide a method. The method includes causing a voltage level of a signal transmitted on a transmission line to be non-linearly modified to reduce a voltage variation at a target level, and providing the modified signal to a receiving circuit that is disposed on the transmission line. In an embodiment, the method includes causing the voltage level of the signal transmitted on the transmission line to be non-linearly modified to reduce a first voltage variation at a first target level corresponding to a first digital value and to reduce a second voltage variation at a second target level corresponding to a second digital value.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: September 1, 2015
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Liav Ben Artsi, Ido Bourstein
  • Patent number: 9089060
    Abstract: Aspects of the disclosure provide a ball grid array (BGA) package. The ball grid array (BGA) package includes an integrated circuit (IC) packaged in the BGA package, first solder ball, a second solder ball and a third solder ball to transmit a first signal, a second signal, and a third signal. The first signal and the second signal are a pair of differential signals. The third solder ball has a substantially equal distance from the first solder ball and the second solder ball, and thus the first solder ball and the second solder ball are in symmetry with regard to the third solder ball.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: July 21, 2015
    Assignee: MARVELL ISRAEL (M.I.S.L.) LTD.
    Inventors: Dan Azeroual, Liav Ben Artsi
  • Publication number: 20150177773
    Abstract: A power supply noise reduction circuit and a power supply noise reduction method are provided. An integrated circuit includes an input node configured to receive a signal via a transmission line. The integrated circuit also includes termination circuitry configured to electrically couple the input node to a power rail of the integrated circuit. The integrated circuit further includes a circuit component coupled to the power rail. The circuit component is configured to bleed off a portion of current on the power rail based on a determination that a voltage on the power rail meets or exceeds a high voltage threshold. The circuit component is also configured to bleed off a smaller portion of the current on the power rail based on a determination that the voltage on the power rail is less than the high voltage threshold.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 25, 2015
    Inventor: Liav Ben Artsi
  • Patent number: 8922246
    Abstract: A system and process overcomes the influence of induced current and/or capacitance in wires and, more particularly, reduces and overcomes induced current and/or capacitance cross-talk between neighboring wire-bonds. A change or toggle in each of a plurality of outputs from a circuit is determined. The change determined for one selected output is compared with the change determined for neighboring outputs. When the change for the neighboring outputs is both the same as that of the selected output, the power of the output or the slew rate of an amplifier that receives the selected output is altered so that the output is increased. When the change for the neighboring outputs is both the opposite of that of the selected output, the power of the output or the slew rate of an amplifier that receives the selected output is altered so that the output is decreased.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: December 30, 2014
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Liav Ben Artsi
  • Patent number: 8884644
    Abstract: The present disclosure provides for a circuit package that can include a signal input port that receives an electronic signal that includes multiple frequency components and a signal output port that outputs the electronic signal. The circuit package can include a trace having multiple portions that have a portion-dependent impedance. The trace can transfer the electronic signal from the signal input port to the signal output port. The present disclosure provides an apparatus to compensate a package trace parasitics, such as parasitic capacitance, to improve signal fidelity over a predetermined frequency range. The apparatus can provide a broadband impedance matching structure that matches the impedance of an I/O cell to the impedance of a printed circuit board and can compensates for the parasitic effects of both the I/O cell, terminals, and other discontinuities that may be present within the package.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 11, 2014
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Liav Ben Artsi
  • Patent number: 8866563
    Abstract: Aspects of the disclosure provide a connector. The connector includes a first signal conductor. The first signal conductor is configured to receive a first electronic signal that includes multiple frequency components. The first signal conductor includes a plurality of conductor portions having portion-dependent impedances. The first signal conductor is configured to transfer the first electronic signal between a via on a circuit board that has a via stub and an electronic device to reduce via stub effects. In addition, in an example, the connector includes a second signal conductor to transfer a second electronic signal. The second electronic signal and the first electronic signal are a pair of differential signals. In an example, the first signal conductor and the second signal conductor have different via stub effects.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: October 21, 2014
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventor: Liav Ben Artsi
  • Publication number: 20140016686
    Abstract: Discussed herein is a semiconductor package and a method of overcoming multiple reflections while transmitting high speed broadband signals through the semiconductor package. The semiconductor package includes at least one trace having a first terminal that is configured to receive a broadband signal and a second terminal configured to output the broadband signal. The semiconductor package includes a stub which is positioned along a longitudinal length of the trace and is configured to reduce broadband reflections in the trace by causing multi-frequency reflections to destructively interfere with at least some broadband reflections in the trace that occur due to impedance discontinuities. The stub parameters such as stub length, stub impedance and the location of the stub along the trace can be determined to minimize signal degradation.
    Type: Application
    Filed: July 16, 2013
    Publication date: January 16, 2014
    Inventor: Liav BEN ARTSI
  • Patent number: 8502342
    Abstract: Circuits, architectures, a system and methods for reducing the effect(s) of cross talk in neighboring I/O signal paths. The circuitry includes input/output (I/O) pads having I/O signal lines coupled thereto, and a capacitor having terminals coupled to the I/O pads and/or signal lines. The method includes transmitting or receiving a signal along a first I/O signal line in an integrated circuit, the first I/O signal line communicating with a first I/O pad on the integrated circuit, and the integrated circuit having a second I/O signal line communicating with a second I/O pad; and capacitively coupling the first signal to the second I/O pad and/or the second I/O signal line, to reduce the effect(s) of cross talk in the second I/O signal line. The present invention can significantly reduce the effects of cross talk in neighboring I/O signal paths, for both input and output signals.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: August 6, 2013
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventor: Liav Ben Artsi
  • Patent number: 8466712
    Abstract: Embodiments of the present disclosure provide an integrated circuit, comprising a first feed forward equalizing (FFE) circuit configured to operate based on receipt of a first common mode voltage; a second FFE circuit coupled to the first FFE circuit, the second FFE circuit configured to operate based on receipt of a second common mode voltage that is different than the first common mode voltage; and a decision circuit coupled to both the first FFE circuit and the second FFE circuit, the decision circuit configured to selectively provide the first common mode voltage to the first FFE circuit or the second common mode voltage to the second FFE circuit.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: June 18, 2013
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Shimon Avitan, Liav Ben Artsi
  • Publication number: 20130022134
    Abstract: Aspects of the disclosure provide a method. The method includes causing a voltage level of a signal transmitted on a transmission line to be non-linearly modified to reduce a voltage variation at a target level, and providing the modified signal to a receiving circuit that is disposed on the transmission line. In an embodiment, the method includes causing the voltage level of the signal transmitted on the transmission line to be non-linearly modified to reduce a first voltage variation at a first target level corresponding to a first digital value and to reduce a second voltage variation at a second target level corresponding to a second digital value.
    Type: Application
    Filed: July 13, 2012
    Publication date: January 24, 2013
    Inventors: Liav BEN ARTSI, Ido Bourstein
  • Patent number: 8319313
    Abstract: Circuits, architectures, a system and methods for reducing the effect(s) of cross talk in neighboring I/O signal paths. The circuitry generally includes first and second input/output (I/O) pads having first and second I/O signal lines coupled thereto, and a capacitor having first and second terminals coupled to the first I/O pad and/or signal line and the second I/O pad and/or signal line, respectively. The method generally comprises the steps of (1) transmitting or receiving a signal along a first I/O signal line in an integrated circuit, the first I/O signal line communicating with a first I/O pad on the integrated circuit, and the integrated circuit having a second I/O signal line communicating with a second I/O pad; and (2) capacitively coupling the first signal to the second I/O pad and/or the second I/O signal line, sufficiently to reduce the effect(s) of cross talk in the second I/O signal line.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: November 27, 2012
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Liav Ben Artsi
  • Patent number: 8274307
    Abstract: The present disclosure provides for a circuit package that can include a signal input port that receives an electronic signal that includes multiple frequency components and a signal output port that outputs the electronic signal. The circuit package can include a trace having multiple portions that have a portion-dependent impedance. The trace can transfer the electronic signal from the signal input port to the signal output port. The present disclosure provides an apparatus to compensate a package trace parasitics, such as parasitic capacitance, to improve signal fidelity over a predetermined frequency range. The apparatus can provide a broadband impedance matching structure that matches the impedance of an I/O cell to the impedance of a printed circuit board and can compensate for the parasitic effects of both the I/O cell, terminals, and other discontinuities that may be present within the package.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: September 25, 2012
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventor: Liav Ben Artsi