Abstract: An apparatus and method to perform error detection in a logic device without performance impact. The apparatus includes an Error Detection Device (EDD) coupled to a memory module and a processor. The memory module connects to the processor. As information transfers from the memory module to the processor, the EDD receives the same information and checks the information for errors. The information may be instructions, data, or control sequences. If the EDD does not detect any errors in the information, the processor is allowed to complete execution of the information. If the EDD detects an error in the information transferred from the memory module, an action is sent to the processor before the erroneous information is executed. Because the error checking is done by the EDD at the same time as the transfer of information from the memory module to the processor, the performance of the system is not impacted.

Abstract: In an integrated circuit having a processing core and at least one memory unit, each memory unit, in addition to the storage cells and addressing circuits, includes apparatus for testing the memory independently from the testing of the processing core. The test apparatus includes a local storage unit to store test procedures and a local processing unit for independently executing the test procedures in response to external control signals. Stress voltages can be applied to the storage cell terminals to determine viability of the storage cell structure. The incorporation of test apparatus as part of the memory permits a tested integrated circuit to be provided that is less expensive than a memory unit that is tested by external test and debug apparatus. The test apparatus permits a threshold voltage for the change in the identification of a stored logic state to be determined in the absence and the presence of a stress voltage without intervention of external signals.

Abstract: In an integrated circuit having a processing core and at least one memory unit, each memory unit, in addition to the storage cells and addressing circuits, includes apparatus for testing the memory independently from the testing of the processing core. The test apparatus includes a local storage unit to store test procedures and a local processing unit for independently executing the test procedures in response to external control signals. Stress voltages can be applied to the storage cell terminals to determine viability of the storage cell structure. The incorporation of test apparatus as part of the memory permits a tested integrated circuit to be provided that is less expensive than a memory unit that is tested by external test and debug apparatus.

Abstract: In an integrated circuit having a processing core and at least one memory unit, each memory unit, in addition to the storage cells and addressing circuits, includes apparatus for testing the memory independently from the testing of the processing core. The test apparatus includes a local storage unit to store test procedures and a local processing unit for independently executing the test procedures in response to external control signals. The incorporation of test apparatus as part of the memory permits a tested integrated circuit to be provided that is less expensive than a memory unit that is tested by external test and debug apparatus.