Patents by Inventor Lichao Hao

Lichao Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10598713
    Abstract: An ESD failure early warning circuit for an integrated circuit is disclosed, including a positive voltage stress generation module, a negative voltage stress generation module, a buck module, a warning output module, capacitors C006, C007, and diodes D001, D002, D003, D004 and D005. The ESD failure early warning circuit can report a warning timely when there is an ESD event in the monitored integrated circuit, to improve the reliability of the device effectively. Moreover, the stress voltage generated by the positive voltage stress generation module and the negative voltage stress generation module is adjustable, so the stress voltage can be set flexibly by a user according to actual condition of the monitored integrated circuit. The present invention has high flexibility and wide application prospect.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 24, 2020
    Assignee: Fifth Electronics Research Institute of Ministry of Industry and Information Technology
    Inventors: Yiqiang Chen, Ang Li, Dengyun Lei, Yunfei En, Lichao Hao, Wenxiao Fang, Bo Hou
  • Patent number: 10503578
    Abstract: An on-chip TDDB degradation monitoring and failure early warning circuit for SoC. A control circuit module converts Q1 and Q0 signals into a switch state control signal and outputs the switch state control signal to a digital conversion module for TDDB performance degradation. A MOS transistor of a first MOS transistor circuit within the digital conversion module for TDDB performance degradation is in a stress state of a supply voltage, and a MOS transistor of a second MOS transistor circuit is in a non-stress state. The first and second MOS transistor circuits output a first frequency value and a second frequency value to the output selection module. The output selection module outputs the first frequency value from the digital conversion module to the counter B for recording, or outputs the second frequency value to the counter A for recording. The counter module determines the degradation level of TDDB performance.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 10, 2019
    Assignee: Fifth Electronics Research Institute of Ministry of Industry and Information Technology
    Inventors: Yiqiang Chen, Dengyun Lei, Yunfei En, Wenxiao Fang, Lichao Hao, Yun Huang, Bo Hou, Yudong Lu
  • Publication number: 20190205196
    Abstract: An on-chip TDDB degradation monitoring and failure early warning circuit for SoC. A control circuit module converts Q1 and Q0 signals into a switch state control signal and outputs the switch state control signal to a digital conversion module for TDDB performance degradation. A MOS transistor of a first MOS transistor circuit within the digital conversion module for TDDB performance degradation is in a stress state of a supply voltage, and a MOS transistor of a second MOS transistor circuit is in a non-stress state. The first and second MOS transistor circuits output a first frequency value and a second frequency value to the output selection module. The output selection module outputs the first frequency value from the digital conversion module to the counter B for recording, or outputs the second frequency value to the counter A for recording. The counter module determines the degradation level of TDDB performance.
    Type: Application
    Filed: November 29, 2016
    Publication date: July 4, 2019
    Applicant: Fifth Electronics Research Institute of Ministry of Industry and Information Technology
    Inventors: Yiqiang Chen, Dengyun Lei, Yunfei En, Wenxiao Fang, Lichao Hao, Yun Huang, Bo Hou, Yudong Lu
  • Publication number: 20190079126
    Abstract: An ESD failure early warning circuit for an integrated circuit is disclosed, including a positive voltage stress generation module, a negative voltage stress generation module, a buck module, a warning output module, capacitors C006, C007, and diodes D001, D002, D003, D004 and D005. The ESD failure early warning circuit can report a warning timely when there is an ESD event in the monitored integrated circuit, to improve the reliability of the device effectively. Moreover, the stress voltage generated by the positive voltage stress generation module and the negative voltage stress generation module is adjustable, so the stress voltage can be set flexibly by a user according to actual condition of the monitored integrated circuit. The present invention has high flexibility and wide application prospect.
    Type: Application
    Filed: November 29, 2016
    Publication date: March 14, 2019
    Applicant: Fifth Electronics Research Institute of Ministry of Industry and Information Technology
    Inventors: Yiqiang Chen, Ang Li, Dengyun Lei, Yunfei En, Lichao Hao, Wenxiao Fang, Bo Hou