Patents by Inventor LI-CHENG HUANG

LI-CHENG HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240174749
    Abstract: This disclosure provides a method for treating a subject afflicted with a tumor or a cancer, wherein the method comprises administering to the subject therapeutically effective amounts of an anti-TIM3 antibody, alone or in combination with an inhibitor of the PD-1 signaling pathway (e.g., anti-PD-1 antibody). In some embodiments, the antibody is administered as a flat dose or a weight-based dose.
    Type: Application
    Filed: September 27, 2023
    Publication date: May 30, 2024
    Applicant: Bristol-Myers Squibb Company
    Inventors: Xiao Min SCHEBYE, Mark J. SELBY, Michelle Minhua HAN, Christine BEE, Andy X. DENG, Anan CHUNTHARAPAI, Brigitte DEVAUX, Huiming LI, Paul O. SHEPPARD, Alan J. KORMAN, Daniel F. ARDOUREL, Ekaterina DEYANOVA, Richard Yu-Cheng HUANG, Guodong CHEN, Michelle Renne KUHNE, Hong-An TRUONG, Poliana PATAH, Jeffrey R. JACKSON, Ronald A. FLEMING
  • Publication number: 20240132904
    Abstract: The present invention relates to a method for producing recombinant human prethrombin-2 protein and having human ?-thrombin activity by the plant-based expression systems.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 25, 2024
    Applicant: PROVIEW-MBD BIOTECH CO., LTD.
    Inventors: Yu-Chia CHANG, Jer-Cheng KUO, Ruey-Chih SU, Li-Kun HUANG, Ya-Yun LIAO, Ching-I LEE, Shao-Kang HUNG
  • Publication number: 20240116148
    Abstract: A tool set includes a tool holder, a tool and a tool rack. The tool has a groove unit. The tool holder has a latch unit that engages the groove unit. The tool rack includes a rack body and a blocking member. When the tool holder is moved away from the rack body after the tool is moved into the rack body by the tool holder and after the blocking member moves to a blocking position, the tool is blocked by the blocking member so that the latch unit is separated from the groove unit and that the tool holder is separated from the tool.
    Type: Application
    Filed: August 28, 2023
    Publication date: April 11, 2024
    Applicant: Jabil Inc.
    Inventors: Harpuneet Singh, Lei Hu, Ying-Chieh Huang, Wei-Hsiu Hsieh, Xiao-Ting Zheng, Chien-Cheng Chu, Tike Hoong Phua, Li Yun Chee
  • Publication number: 20240096997
    Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first source/drain region disposed in a PFET region and a second source/drain region disposed in an NFET region. The second source/drain region comprises a dipole region. The structure further includes a first silicide layer disposed on and in contact with the first source/drain region, a second silicide layer disposed on and in contact with the first silicide layer, and a third silicide layer disposed on and in contact with the dipole region of the second source/drain region. The first, second, and third silicide layers include different materials. The structure further includes a first conductive feature disposed over the first source/drain region, a second conductive feature disposed over the second source/drain region, and an interconnect structure disposed on the first and second conductive features.
    Type: Application
    Filed: January 15, 2023
    Publication date: March 21, 2024
    Inventors: Po-Chin Chang, Lin-Yu Huang, Li-Zhen Yu, Yuting Cheng, Sung-Li Wang, Pinyen Lin
  • Publication number: 20240071911
    Abstract: A semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. A method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.
    Type: Application
    Filed: January 31, 2023
    Publication date: February 29, 2024
    Inventors: Harry-Haklay Chuang, Wen-Tuo Huang, Li-Feng Teng, Wei-Cheng Wu, Yu-Jen Wang
  • Publication number: 20220077347
    Abstract: Disclosed is a multi-quantum well structure including a stress relief layer, an electron-collecting layer disposed on the stress relief layer, and an active layer including a first active layer unit that is disposed on the electron-collecting layer. The first active layer unit includes potential barrier sub-layers and potential well sub-lavers being alternately stacked, in which at least one of the potential barrier sub-layers has a GaN/Alx1Iny1Ga(1-x1-y1)N stack, where 0<x1?1 and 0?y1<1. An LED device including the multi-quantum well structure is also disclosed.
    Type: Application
    Filed: November 17, 2021
    Publication date: March 10, 2022
    Inventors: HAN JIANG, YUNG-LING LAN, WEN-PIN HUANG, CHANGWEI SONG, LI-CHENG HUANG, FEILIN XUN, CHAN-CHAN LING, CHI-MING TSAI, CHIA-HUNG CHANG
  • Patent number: 11189751
    Abstract: Disclosed is a multi-quantum well structure including a stress relief layer, an electron-collecting layer disposed on the stress relief layer, and an active layer including a first active layer unit that is disposed on the electron-collecting layer. The first active layer unit includes potential barrier sub-layers and potential well sub-layers being alternately stacked, in which at least one of the potential barrier sub-layers has a GaN/Alx1Iny1Ga(1-x1-y1)N/GaN stack, where 0<x1?1 and 0?y1<1, and for the remainder of the potential barrier sub-layers, each of the potential barrier sub-layers is a GaN layer. An LED device including the multi-quantum well structure is also disclosed.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: November 30, 2021
    Assignee: Xiamen San'An Optoelectronics Co., Ltd.
    Inventors: Han Jiang, Yung-Ling Lan, Wen-Pin Huang, Changwei Song, Li-Cheng Huang, Feilin Xun, Chan-Chan Ling, Chi-Ming Tsai, Chia-Hung Chang
  • Publication number: 20200052155
    Abstract: Disclosed is a multi-quantum well structure including a stress relief layer, an electron-collecting layer disposed on the stress relief layer, and an active layer including a first active layer unit that is disposed on the electron-collecting layer. The first active layer unit includes potential barrier sub-layers and potential well sub-layers being alternately stacked, in which at least one of the potential barrier sub-layers has a GaN/Alx1Iny1Ga(1-x1-y1)N/GaN stack, where 0<x1?1 and 0?y1<1, and for the remainder of the potential barrier sub-layers, each of the potential barrier sub-layers is a GaN layer. An LED device including the multi-quantum well structure is also disclosed.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: HAN JIANG, YUNG-LING LAN, WEN-PIN HUANG, CHANGWEI SONG, LI-CHENG HUANG, FEILIN XUN, CHAN-CHAN LING, CHI-MING TSAI, CHIA-HUNG CHANG