Patents by Inventor Licheng M. Han

Licheng M. Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10349526
    Abstract: An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: July 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Byron Lovell Williams, Asad Mahmood Haider, Licheng M. Han
  • Publication number: 20190182961
    Abstract: An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 13, 2019
    Inventors: Byron Lovell Williams, Asad Mahmood Haider, Licheng M. Han
  • Patent number: 10251280
    Abstract: An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: April 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Byron Lovell Williams, Asad Mahmood Haider, Licheng M. Han
  • Publication number: 20150187488
    Abstract: An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.
    Type: Application
    Filed: December 19, 2014
    Publication date: July 2, 2015
    Inventors: Byron Lovell Williams, Asad Mahmood Haider, Licheng M. Han
  • Publication number: 20120211884
    Abstract: A method and structure for forming a semiconductor device, for example a device including a wafer chip scale package (WCSP), can include the formation of at least one conductive layer which contacts a bond pad. The at least one conductive layer can be patterned using a first mask, then a passivation layer can be formed over the patterned at least one conductive layer. The passivation layer can be patterned using a second mask to expose the at least one conductive layer, then a conductive layer such as a solder ball, conductive bump, metal-filled paste, or another conductor is formed on the at least one conductive layer. The method can result in a structure which is formed using a reduced number of mask steps.
    Type: Application
    Filed: February 23, 2011
    Publication date: August 23, 2012
    Inventors: Frank Stepniak, Christopher Daniel Manack, Licheng M. Han
  • Patent number: 6424044
    Abstract: A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: July 23, 2002
    Assignees: Chartered Semiconductor Manufacturing Ltd., Institute of Microelectronics
    Inventors: Licheng M. Han, Xu Yi, Joseph Zhifeng Xie, Mei Sheng Zhou, Simon Chooi
  • Publication number: 20020076918
    Abstract: A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.
    Type: Application
    Filed: January 18, 2002
    Publication date: June 20, 2002
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Licheng M. Han, Yi Xu, Joseph Zhiefeng Xie, Mei Sheng Zhou, Simon Chooi
  • Patent number: 6352921
    Abstract: A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: March 5, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Licheng M. Han, Yi Xu, Joseph Zhifeng Xie, Mei Sheng Zhou, Simon Chooi