Abstract: A method of fabricating non-volatile memory devices integrated in a semiconductor substrate is presented. The memory devices include a matrix of non-volatile memory cells, each having floating-gate MOS transistors with associated gate electrodes, as well as control circuitry formed of MOS transistors also having gate electrodes. The method includes forming gate electrodes above the substrate, then depositing a first dielectric layer onto the entire exposed surface. Next the first dielectric layer is etched back to form isolating spacers on the side walls of the gate electrodes of the matrix cells. Then a second dielectric layer is deposited onto the entire exposed surface, and the memory matrix is overlaid with a protective layer. In the circuitry area, the second dielectric layer is etched back to form isolating spacers on the side walls of the gate electrodes of the circuitry transistors, while the floating-gate MOS transistors are protected.