Abstract: A sensor for biomolecules includes a silicon fin comprising undoped silicon; a source region adjacent to the silicon fin, the source region comprising heavily doped silicon; a drain region adjacent to the silicon fin, the drain region comprising heavily doped silicon of a doping type that is the same doping type as that of the source region; and a layer of a gate dielectric covering an exterior portion of the silicon fin between the source region and the drain region, the gate dielectric comprising a plurality of antibodies, the plurality of antibodies configured to bind with the biomolecules, such that a drain current flowing between the source region and the drain region varies when the biomolecules bind with the antibodies.

Abstract: A structure and a method for a semiconductor including a nanostructure semiconductor channel. The semiconductor may include a dielectric and an electrode, the electrode attached to the dielectric, a semiconductor channel may be disposed proximate to the dielectric, wherein the semiconductor channel has an electric mobility and is configured to have at least one dimension, and wherein the dielectric may be configured to apply a force at the at least one dimension.

Abstract: An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.

Abstract: Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.

Abstract: A nanowire product and process for fabricating it has a wafer with a buried oxide (BOX) upper layer in which a well is formed and the ends of a nanowire are on the BOX layer forming a beam that spans the well. A mask coating is formed on the upper surface of the BOX layer leaving an uncoated window over a center part of the beam and also forming a mask coating around the beam intermediate ends between each end of the beam center part and a side wall of the well. Applying oxygen through the window thins the beam center part while leaving the wire intermediate ends over the well thicker and having a generally arched shape. A thermal oxide coating can be placed on the wire and also the mask on the BOX layer before oxidation.

Abstract: Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.

Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.

Abstract: In one embodiment, a semiconductor nanowire having a monotonically increasing width with distance from a middle portion toward adjoining semiconductor pads is provided. A semiconductor link portion having tapered end portions is lithographically patterned. During the thinning process that forms a semiconductor nanowire, the taper at the end portions of the semiconductor nanowire provides enhanced mechanical strength to prevent structural buckling or bending. In another embodiment, a semiconductor nanowire having bulge portions are formed by preventing the thinning of a semiconductor link portion at pre-selected positions. The bulge portions having a greater width than a middle portion of the semiconductor nanowire provides enhanced mechanical strength during thinning of the semiconductor link portion so that structural damage to the semiconductor nanowire is avoided during thinning.

Abstract: A p-type semiconductor nanowire transistor is formed on the first semiconductor nanowire and an n-type semiconductor nanowire transistor is formed on the second semiconductor nanowire. The first and second semiconductor nanowires have a rectangular cross-sectional area with different width-to-height ratios. The type of semiconductor nanowires for each semiconductor nanowire transistor is selected such that top and bottom surfaces provide a greater on-current per unit width than sidewall surfaces in a semiconductor nanowire having a greater width-to-height ratio, while sidewall surfaces provide a greater on-current per unit width than top and bottom surfaces in the other semiconductor nanowire having a lesser width-to-height ratio. Different types of stress-generating material layers may be formed on the first and second semiconductor nanowire transistors to provide opposite types of stress, which may be employed to enhance the on-current of the first and second semiconductor nanowire transistors.

Abstract: Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.

Abstract: Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.

Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

Abstract: A semiconductor nanowire is coated with a chemical coating layer that selectively attaches to the semiconductor material and which forms a dye in a chemical reaction. The dye layer comprises a material that absorbs electromagnetic radiation. A portion of the absorbed energy induces electronic excitation in the chemical coating layer from which additional free charge carriers are temporarily donated into the semiconductor nanowire. Thus, the conductivity of the semiconductor nanowire increases upon illumination on the dye layer. The semiconductor nanowire, and the resulting dye layer collective operate as a detector for electromagnetic radiation.

Abstract: A semiconductor nanowire is coated with a chemical coating layer that comprises a functional material which modulates the quantity of free charge carriers within the semiconductor nanowire. The outer surface of the chemical coating layer includes a chemical group that facilitates bonding with molecules to be detected through electrostatic forces. The bonding between the chemical coating layer and the molecules alters the electrical charge distribution in the chemical coating layer, which alters the amount of the free charge carriers and the conductivity in the semiconductor nanowire. The coated semiconductor nanowire may be employed as a chemical sensor for the type of chemicals that bonds with the functional material in the chemical coating layer. Detection of such chemicals may indicate pH of a solution, a vapor pressure of a reactive material in gas phase, and/or a concentration of a molecule in a solution.

Abstract: Non-chemically amplified radiation sensitive resist compositions containing silicon are especially useful for lithographic applications, especially E-beam lithography. More particularly, radiation-sensitive resist compositions comprising a polymer having at least one silicon-containing moiety and at least one radiation-sensitive moiety cleavable upon radiation exposure to form aqueous base soluble moiety can be used to pattern sub-50 nm features with little or no blur.

Abstract: A micro-electrical mechanical oscillator has a resonant frequency of oscillation that is varied by application of heat. The resonant frequency is varied at a frequency different from the resonant frequency of the oscillator to amplify oscillations. In one embodiment, the oscillator is disc of material supported by a pillar of much smaller diameter than the disc. The periphery of the disc is heated by a laser to provide a time varying shift of the resonant frequency (or equivalently the stiffness) of the disc. Feedback from movement of the disc is used to modulate the intensity of the laser, and thus the stiffness of the disc to provide parametric amplification of sensed vibrations, using heating as a pump. Various other shapes of micro-electrical mechanical oscillators are used in other embodiment, including an array of such oscillators on a substrate, each having different resonant frequencies.

Abstract: The negative resist compositions especially suitable for electron beam-based lithographic processes are obtained by using a polymeric component containing first silsesquioxane moieties functionalized with a first reactive group having a first crosslinking reactivity and a first dissolution rate in aqueous alkaline solutions, and second silsesquioxane moieties functionalized with a second reactive group having a second crosslinking reactivity and a second dissolution rate in aqueous alkaline solutions, said reactivities being different from one another and said dissolution rates being different from one another. These negative resists enable improved negative lithographic processes, especially in the context of mask-making and direct-write techniques using electron beam lithography. The negative resists are also useful more generally in methods of forming patterned material features and advantageously show reduced incidence of image collapse at smaller groundrules.

Abstract: The negative resist compositions especially suitable for electron beam-based lithographic processes are obtained by using a polymeric component containing first silsesquioxane moieties functionalized with a first reactive group having a first crosslinking reactivity and a first dissolution rate in aqueous alkaline solutions, and second silsesquioxane moieties functionalized with a second reactive group having a second crosslinking reactivity and a second dissolution rate in aqueous alkaline solutions, said reactivities being different from one another and said dissolution rates being different from one another. These negative resists enable improved negative lithographic processes, especially in the context of mask-making and direct-write techniques using electron beam lithography. The negative resists are also useful more generally in methods of forming patterned material features and advantageously show reduced incidence of image collapse at smaller groundrules.

Abstract: The present invention discloses a resist composition and a method of forming a material structure having a pattern containing features having a dimension of about 40 nm or less by using the inventive resist. The inventive resist comprises a polymer and a photoacid generator. The polymer of the present invention comprises pendant polar moieties, pendant fluoroalcohol moieties, and a backbone containing SiO moieties. In the present invention, at least a portion of the polar moieties are protected with acid labile moieties having a low activation energy. It is preferred that some, but not all, of the pendant fluoroalcohol moieties are protected with acid labile moieties having a low activation energy.

Abstract: A method of increasing a quality factor for a micromechanical resonator uses a laser beam to anneal the micromechanical resonator. In one embodiment, the micromechanical oscillator is formed by fabricating a mushroom shaped silicon oscillator supported by a substrate via a pillar. The laser beam is focused on a periphery of the mushroom shaped silicon oscillator to modify the surface of the mushroom shaped silicon oscillator. In a further embodiment, the mushroom shaped oscillator is a silicon disk formed on a sacrificial layer. Portions of the sacrificial layer are removed to free the periphery of the disk and leave a supporting pillar at the center of the disk. In further embodiments, different type resonators may be used.