Patents by Inventor Liding Yin

Liding Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power-on-reset circuit with brown-out reset for multiple power supplies
    Patent number: 8106688
    Abstract: A power-on reset circuit includes a first circuit and a second circuit. The first circuit include a first NMOS transistor having a gate controlled by a low voltage supply VDD_L, a resistor connected between the source of the first NMOS transistor and a voltage supply VSS that is lower than VDD_L, and one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor. The second circuit includes a first PMOS transistor having a source connected to VDD_L, a second PMOS transistor having a source connected to the drain of first PMOS transistor, a second NMOS transistor connected between the drain of the second PMOS transistor and VSS, and an inverter configured to output a signal in response to the power on of the high voltage supply VDD_H and the low voltage supply VDD_L.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: January 31, 2012
    Assignee: Smartech Worldwide Limited
    Inventors: Haitao Huang, Min Zhang, Liding Yin
  • POWER-ON-RESET CIRCUIT WITH BROWN-OUT RESET FOR MULTIPLE POWER SUPPLIES
    Publication number: 20110115533
    Abstract: A power-on reset circuit includes a first circuit and a second circuit. The first circuit include a first NMOS transistor having a gate controlled by a low voltage supply VDD_L, a resistor connected between the source of the first NMOS transistor and a voltage supply VSS that is lower than VDD_L, and one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor. The second circuit includes a first PMOS transistor having a source connected to VDD_L, a second PMOS transistor having a source connected to the drain of first PMOS transistor, a second NMOS transistor connected between the drain of the second PMOS transistor and VSS, and an inverter configured to output a signal in response to the power on of the high voltage supply VDD_H and the low voltage supply VDD_L.
    Type: Application
    Filed: November 18, 2009
    Publication date: May 19, 2011
    Inventors: Haitao Huang, Min Zhang, Liding Yin