Patents by Inventor Lidwine Martinot

Lidwine Martinot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8358988
    Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: January 22, 2013
    Assignee: MediaTek Inc.
    Inventors: Lidwine Martinot, Deepak Mathew, Krishnan Vishwanathan, Eric Aardoom, Aiguo Yan, Timothy Fisher-Jeffes
  • Publication number: 20120269175
    Abstract: A TD-SCDMA receiver includes a joint detector that receives an input signal from a transceiver. The joint detector analyzes the input signal to determine whether one or more neighboring cells are used in conjunction with a servicing cell. Also, the joint detector assigns a first matrix that includes all coded channels including those associated with the one or neighboring cells so as to formulate a channel matrix. The joint detector uses a selective ratio that has been minimized to define elements of the first matrix so as to efficiently control the bit-width of the joint detector.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 25, 2012
    Inventors: Aiguo Yan, Yonggang Hao, Lidwine Martinot, Marko Kocic
  • Patent number: 7953958
    Abstract: A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: May 31, 2011
    Assignee: MediaTek Inc.
    Inventors: John Zijun Shen, Paul D. Krivacek, Thomas J. Barber, Jr., Lidwine Martinot, Aiguo Yan, Marko Kocic
  • Patent number: 7949925
    Abstract: A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: May 24, 2011
    Assignee: MediaTek Inc.
    Inventors: Lidwine Martinot, Aiguo Yan, Marko Kocic, Thomas J. Barber, Jr., John Zijun Shen
  • Patent number: 7924948
    Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals. The joint detection system includes a programmable digital signal processor (DSP) configured to generate initial channel estimates corresponding to propagation channels, wherein each of the initial channel estimates includes a plurality of values. The programmable DSP is further configured to determine one or more pre-scaling factors for one or more of the initial channel estimates. The pre-scaling factors are at least partially based on at least one of the plurality of values of one or more of the initial channel estimates. The programmable DSP is further configured to pre-scale the initial channel estimates by the pre-scaling factors.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: April 12, 2011
    Assignee: MediaTek Inc.
    Inventors: Marko Kocic, Aiguo Yan, Lidwine Martinot, Thomas J. Barber, Jr., John Zijun Shen
  • Patent number: 7916841
    Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: March 29, 2011
    Assignee: MediaTek Inc.
    Inventors: Aiguo Yan, Lidwine Martinot, Marko Kocic, Paul D. Krivacek, Thomas J. Barber, Jr., John Zijun Shen
  • Patent number: 7388936
    Abstract: A receiver unit includes a prefilter that receives as one of the inputs a channel impulse response (CIR) estimation data set and removes unnecessary data information from the CIR estimation data set and filters input signal so to form a first output data set. An equalizer core receives the first output data set and based on computed CIR length and SNR value of the first output data set so as to determine which portion of the first output data set are assigned to at least one of at least two low complexity equalization modules used for processing.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: June 17, 2008
    Assignee: Mediatek, Inc.
    Inventors: Marko Kocic, Lidwine Martinot, Zoran Zvonar
  • Publication number: 20080089448
    Abstract: A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.
    Type: Application
    Filed: October 11, 2006
    Publication date: April 17, 2008
    Applicant: Analog Devices, Inc.
    Inventors: Lidwine Martinot, Aiguo Yan, Marko Kocic, Thomas J. Barber, John Zijun Shen
  • Publication number: 20080080638
    Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.
    Type: Application
    Filed: October 11, 2006
    Publication date: April 3, 2008
    Applicant: Analog Devices, Inc.
    Inventors: Aiguo Yan, Lidwine Martinot, Marko Kocic, Paul D. Krivacek, Thomas J. Barber, John Zijun Shen
  • Publication number: 20080080645
    Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals. The joint detection system includes a programmable digital signal processor (DSP) configured to generate initial channel estimates corresponding to propagation channels, wherein each of the initial channel estimates includes a plurality of values. The programmable DSP is further configured to determine one or more pre-scaling factors for one or more of the initial channel estimates. The pre-scaling factors are at least partially based on at least one of the plurality of values of one or more of the initial channel estimates. The programmable DSP is further configured to pre-scale the initial channel estimates by the pre-scaling factors.
    Type: Application
    Filed: October 11, 2006
    Publication date: April 3, 2008
    Applicant: Analog Devices, Inc.
    Inventors: Marko Kocic, Aiguo Yan, Lidwine Martinot, Thomas J. Barber, John Zijun Shen
  • Publication number: 20080080542
    Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 3, 2008
    Applicant: Analog Devices, Inc.
    Inventors: Krishnan Vishwanathan, Deepak Mathew, Eric Aardoom, Lidwine Martinot, Aiguo Yan, Timothy Fisher-Jeffes, Paul D. Krivacek
  • Publication number: 20080080443
    Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 3, 2008
    Applicant: Analog Devices, Inc.
    Inventors: Lidwine Martinot, Deepak Mathew, Krishnan Vishwanathan, Eric Aardoom, Aiguo Yan, Timothy Fisher-Jeffes
  • Publication number: 20080080468
    Abstract: A joint detection system is configured to perform joint detection of received signals and includes ajoint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.
    Type: Application
    Filed: June 12, 2007
    Publication date: April 3, 2008
    Applicant: Analog Devices, Inc.
    Inventors: John Zijun Shen, Paul D. Krivacek, Thomas J. Barber, Lidwine Martinot, Aiguo Yan, Marko Kocic
  • Patent number: 7266160
    Abstract: Although DC offset reduction schemes can be applied in the analog domain, the residual static DCO in baseband is still present, significantly influencing the performance of high-level modulation schemes employed by recent high-data-rate wireless communications standards. In order to achieve satisfactory performance, DCO compensation algorithms are required in the digital domain. One such algorithm was developed which is based on joint estimation of the Channel Impulse Response (CIR) and the static DCO and ensures satisfactory performance of EDGE modem with direct conversion radio architectures. A further modification of the joint estimation algorithm, the so-called “perturbed joint L”, results in further improvement in the performance of the EDGE equalizer in critical fading channels.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: September 4, 2007
    Assignee: Analog Devices, Inc.
    Inventors: Marko Kocic, Lidwine Martinot, Zoran Zvonar
  • Publication number: 20050204208
    Abstract: A receiver unit includes a prefilter that receives as one of the inputs a channel impulse response (CIR) estimation data set and removes unnecessary data information from the CIR estimation data set and filters input signal so to form a first output data set. An equalizer core receives the first output data set and based on computed CIR length and SNR value of the first output data set so as to determine which portion of the first output data set are assigned to at least one of at least two low complexity equalization modules used for processing.
    Type: Application
    Filed: November 12, 2004
    Publication date: September 15, 2005
    Inventors: Marko Kocic, Lidwine Martinot, Zoran Zvonar
  • Publication number: 20050084039
    Abstract: Although DC offset reduction schemes can be applied in the analog domain, the residual static DCO in baseband is still present, significantly influencing the performance of high-level modulation schemes employed by recent high-data-rate wireless communications standards. In order to achieve satisfactory performance, DCO compensation algorithms are required in the digital domain. One such algorithm was developed which is based on joint estimation of the Channel Impulse Response (CIR) and the static DCO and ensures satisfactory performance of EDGE modem with direct conversion radio architectures. A further modification of the joint estimation algorithm, the so-called “perturbed joint L”, results in further improvement in the performance of the EDGE equalizer in critical fading channels.
    Type: Application
    Filed: October 20, 2003
    Publication date: April 21, 2005
    Inventors: Marko Kocic, Lidwine Martinot, Zoran Zvonar