Abstract: An apparatus for converting and scaling non-interlaced VGA signal to interlaced TV signal suitable to be displayed on a TV video screen is disclosed. The apparatus includes an analog to digital converter, a vertical scaling down device, a vertical scaling up device, a horizontal scaling down device, a horizontal scaling up device, a memory unit, a memory controller, and a digital to analog converter. The apparatus is capable of scaling the non-interlaced VGA signal to interlaced TV signal with any desired scaling size both in horizontal direction and in vertical direction to meet the requirement of displaying operation of the TV screen.

Abstract: A bit-reversing method and system are disclosed for linearly scaling an image frame horizontally, vertically or both. The system includes a counter circuit for outputting the current frame-column number of the currently scanned pixel and the current frame-row number of the currently scanned frame-row. The numbers are bit reversed in a converter circuit. The bit-reversed current frame-column number is compared in a comparator circuit to a horizontal scaling constant which equals the number of pixels to be discarded in each frame-row of the image frame. The bit-reversed current frame-row number is compared in the comparator circuit to a vertical scaling constant which equals the number of frame-rows of the image frame to be discarded. If the bit-reversed current frame-row number is greater than the vertical scaling constant then the comparator circuit outputs appropriate signals to a scaling controller and an address generator for storing the currently scanned frame-row in a frame buffer.

Abstract: An converter apparatus to convert the (X, Y) coordinate of the two-dimensional screen position of a pixel to a linear address. The converter apparatus, which can be used with a variety of video displays of various resolutions including 1280.times.1024, 1152.times.900, 640.times.480, 1024.times.768, 1600.times.1280, and 800.times.600, contains three circuits in parallel disposition to receive and process various portions of the X and Y bits, and to output a Z-bit linear address. The first circuit mainly contains a multiplexer and it receives lower X bits as inputs; the second circuit contains a plurality of adders and multiplexers and a logical operation circuit, and it receives higher X bits and lower Y bits as inputs; and the third circuit mainly contains a multiplexer and it receives higher Y bits and at least a portion of the lower Y bits as inputs. The converter apparatus does not require a system CPU thus very high speed conversion can be achieved.

Abstract: A host computer, a graphics processor which receives and executes commands generated by the host computer, a display memory for storing display data, and a display device for displaying the display data are provided. A graphics context is also provided in which the parameters of a current image are stored. A processing unit for receiving and executing the graphics commands issued by the host computer and for converting the parameters stored in the graphics context into the display data, and a drawing unit for storing the display data in the display memory are also provided. Furthermore, a shared memory is provided which is directly accessible to the host computer so that it can write the parameters of a next graphics command into the shared memory while the graphics processor is executing a current command. The shared memory is also directly accessible to the graphics processor so that it can receive the parameters of the next graphics command to be executed directly from the shared memory.