Patents by Inventor Lie Wang

Lie Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210132614
    Abstract: A method and apparatus for controlling an autonomous vehicle. The method may include: acquiring vehicle traveling environment information; determining an intended traveling state of the autonomous vehicle based on the vehicle traveling environment information; and in response to detecting an interactive operation of a target user for the intended traveling state, generating a traveling state adjustment instruction corresponding to the interactive operation to control the autonomous vehicle to adjust a traveling state.
    Type: Application
    Filed: December 10, 2020
    Publication date: May 6, 2021
    Inventors: Yue WANG, Ruihao MIN, Jingjing XUE, Yingnan LIU, Donghui SHEN, Lie CHENG
  • Publication number: 20190222044
    Abstract: Charging/recharging systems and charge status indicators are provided. In one implementation, a charge status indicator includes a charge sensing device configured to sense the charge of a rechargeable power supply. The charge status indicator further includes a detection device configured to compare the sensed charge with a plurality of predetermined levels in order to determine one of a plurality of capacity ranges of the rechargeable power supply. The charge status indicator also includes a first light emitting diode (LED), a second LED, and a switching circuit configured to switch the first and second LEDs on and off using a plurality of predefined illumination patterns to indicate the capacity range of the rechargeable power supply.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Inventors: Jiaqi Liu, Janna Yu, Lie Wang, Larry Ramsey-Macomber, Stephen J. Colavito, Derrik Cheng, Charles Joseph Cunningham, IV, Ka Man Au, Joseph Livingston, HongJian Jin, David Wiltz, SR., Gavin Di
  • Patent number: 9479464
    Abstract: A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in to which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: October 25, 2016
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Chi-Lie Wang, BaoDong Hu, Scott W. Mitchell
  • Patent number: 9348789
    Abstract: A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: May 24, 2016
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Chi-Lie Wang, Baodong Hu, Scott W. Mitchell
  • Patent number: 9203769
    Abstract: A method and apparatus for congestion and fault management with time-to-live (TTL) have been disclosed. Each time a packet is transferred into an Egress Port's Final Buffer, an associated TTL Timeout Counter will be loaded with a value. If the packet cannot be transferred out of the Egress Port before TTL timeout, it will be purged by removing a memory buffer pointer from the corresponding Virtual Output Queue (VOQ) entry.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: December 1, 2015
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Chi-Lie Wang, Jason Mo
  • Patent number: 8902765
    Abstract: A method and apparatus for congestion and fault management with time-to-live (TTL) have been disclosed. Each time a packet is transferred into an Egress Port's Final Buffer, an associated TTL Timeout Counter will be loaded with a value. If the packet cannot be transferred out of the Egress Port before TTL timeout, it will be purged by removing a memory buffer pointer from the corresponding Virtual Output Queue (VOQ) entry.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: December 2, 2014
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chi-Lie Wang, Jason Z Mo
  • Patent number: 8850089
    Abstract: A method and apparatus for unified final buffer with pointer-based and page-based scheme for traffic optimization have been disclosed.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: September 30, 2014
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chi-Lie Wang, Jason Z. Mo
  • Patent number: 8625621
    Abstract: A serial buffer transports packets through queues capable of operating in a packet mode or a raw data mode. In packet mode, entire packets are stored in a queue. In raw data mode, packet header/delimiter information is not stored in the queue (only packet data is stored). Packets can be transferred out of a queue in response to a slave read request. The serial buffer constructs a packet header in response to the slave read request, and retrieves a specified amount of packet data from the selected queue. The serial buffer also transfers out packets as a bus master when a water level exceeds a water mark within a queue. The serial buffer constructs packet headers for these bus master transfers, which may be performed in a flush mode or a non-flush mode (in packet mode), or in a flush mode (in raw data mode).
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: January 7, 2014
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chi-Lie Wang, Jason Z. Mo
  • Patent number: 8571050
    Abstract: A method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer (RT) and continuous transfer (CT) modes have been disclosed where outstanding packets to be processed is through a Retransmission Mapper with a VOQ read pointer realignment that can quickly optimize network traffic with multiple VCs and mixed RT/CT modes.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: October 29, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chi-Lie Wang, Ming-Shiung Chen, Jason Z Mo
  • Patent number: 8516163
    Abstract: A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: August 20, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chi-Lie Wang, Bertan Tezcan
  • Patent number: 8358655
    Abstract: A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: January 22, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chi-Lie Wang, BaoDong Hu, Scott W. Mitchell
  • Patent number: 8332554
    Abstract: In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: December 11, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Baranitharan Subbiah, Sanjay Katabathuni, Shoby A. Cherian, Chi-Lie Wang, Maria Hu, Sudhakar Rao, Kap Soh, Scott W. Mitchell, Raymond Su, Lomberto P. Jimenez
  • Patent number: 8325723
    Abstract: A method and apparatus for dynamic traffic management with packet classification have been disclosed where packet size, variation, and count may be used to select credit or packet based arbitration.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: December 4, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chi-Lie Wang, Jason Z Mo
  • Patent number: 8320392
    Abstract: A method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switches have been disclosed where a buffer availability is based on a programmable reservation size for dynamic allocation.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: November 27, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chi-Lie Wang, Jason Z Mo
  • Patent number: 8312241
    Abstract: Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block, the memory block is removed from the used buffer pointer list and added to a request buffer pointer list. If a corresponding response packet is received within a timeout period, the memory block is transferred from the request buffer pointer list to the free buffer pointer list. Otherwise, the memory block is transferred from the request buffer pointer list to the used buffer pointer list.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: November 13, 2012
    Assignee: Integrated Device Technology, inc.
    Inventors: Chi-Lie Wang, Jason Z. Mo
  • Patent number: 8312190
    Abstract: A serial buffer includes a first port configured to operate in accordance with a first serial protocol and a second port configured to operate in accordance with a second serial protocol. A first translation circuit of the serial buffer allows packets received on the first port to be translated to the second serial protocol, and then transferred to the second port. A second translation circuit of the serial buffer allows packets received on the second port to be translated to the first serial protocol, and then transferred to the first port. Translations may be performed in response to information included in the headers of the received packets, including source ID values, destination ID values and/or case number values.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: November 13, 2012
    Assignee: Integrated Device Technology, inc.
    Inventors: Chi-Lie Wang, Jason Z. Mo
  • Patent number: 8291246
    Abstract: A power management circuit for managing power of a network interface is provided. The network interface includes a medium interface unit coupled to a network media supporting at least a high speed protocol and a lower speed protocol. The power management logic includes logic to determine that an event signalling entry of the medium interface unit into the lower speed protocol has occurred; and logic to force the medium interface unit into the lower speed protocol in response to a determination that the event has occurred.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: October 16, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Nathan Henderson, Chi-Lie Wang, Baodong Hu
  • Patent number: 8254399
    Abstract: A method and apparatus for adaptive buffer management for traffic optimization on switches have been disclosed where pattern injection and traffic monitoring with forced congestion allows optimizing buffers while accounting for actual system delays.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: August 28, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chi-Lie Wang, Jason Z Mo
  • Patent number: 8238339
    Abstract: A method and apparatus for selective packet discard have been disclosed where two bits are added to a packet to indicate various discard options.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: August 7, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chi-Lie Wang, Jason Z Mo
  • Patent number: 8213448
    Abstract: A serial buffer monitors an incoming stream of packets to identify single missing packets and multiple consecutive missing packets. Upon detecting multiple consecutive missing packets, an interrupt is generated, thereby stopping the data transfer. Upon detecting a single missing packet, a single missing packet identifier is inserted into the packet header of the packet that resulted in identification of the single missing packet. The incoming packets, including any inserted single missing packet identifiers, are written to a queue. When the water level reaches the water mark of the queue, the stored packets are read to create an outgoing packet stream. When a packet read from the queue includes an inserted single missing packet identifier, a dummy packet (e.g., a packet having a data payload of all zeros) is inserted into the outgoing packet stream. As a result, real-time applications are capable of processing the outgoing packet stream in a constant fashion.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: July 3, 2012
    Assignee: Integrated Device Technology, inc.
    Inventors: Chi-Lie Wang, Jason Z. Mo, Calvin Nguyen, Bertan Tezcan