Abstract: A method and a system for comprehensively evaluating reliability of a multi-chip parallel IGBT module are provided. The method includes: establishing a gate-emitter voltage reliability model of the multi-chip parallel IGBT module, performing a chip fatigue failure test, and selecting a gate-emitter voltage as a failure characteristic quantity; establishing a transconductance reliability model of the multi-chip parallel IGBT module, performing a bonding wire shedding failure test, and selecting a transmission characteristic curve of the module as a failure characteristic quantity; using a Pearson correlation coefficient to characterize a degree of health of the IGBT module, and respectively calculating degrees of health PPMCCC and PPMCCB in different degrees of chip fatigue and bonding wire shedding failure states; and comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to PPMCCC and PPMCCB.

Abstract: A method and system for predicting an insulated gate bipolar transistor (IGBT) lifetime based on compound failure mode coupling are provided. First, a simultaneous failure probability model of a bonding wire and a solder layer is calculated. Next, expectancy of the simultaneous failure probability model is calculated and recorded as a lifetime under a coupling effect. A coupling function relation is established. A lifetime of the solder layer and a lifetime of the bonding wire are predicted. An IGBT lifetime prediction model not taking the coupling effect into account is established. An IGBT lifetime prediction model taking the coupling effect into account is established. In the disclosure, the lifetime of the IGBT module under the coupling effect of the solder layer and the bonding wire may be accurately predicted.

Abstract: The present disclosure discloses a rolling ring shrink fitting tool for rotary equipment, including a lifting frame; a movement slot is formed in a bottom surface of a top of the lifting frame; an output end of a first motor is connected with a main gear; guide rollers are embedded in a lifting seat through bearings; shrink fitting plates are two semicircular structures; lifting lugs are welded on outer sides of the shrink fitting plates; tooth rings are arranged outside the shrink fitting plates; stop rods are fixed on inner walls of the tooth rings; supporting screw rods are embedded at sunken positions on inner walls of the shrink fitting plates through bearings.

Abstract: The present disclosure discloses a rolling ring shrink fitting tool for rotary equipment, including a lifting frame; a movement slot is formed in a bottom surface of a top of the lifting frame; an output end of a first motor is connected with a main gear; guide rollers are embedded in a lifting seat through bearings; shrink fitting plates are two semicircular structures; lifting lugs are welded on outer sides of the shrink fitting plates; tooth rings are arranged outside the shrink fitting plates; stop rods are fixed on inner walls of the tooth rings; supporting screw rods are embedded at sunken positions on inner walls of the shrink fitting plates through bearings.

Abstract: A reliability evaluation method and system for a microgrid inverter IGBT based on segmented long short-term memory (LSTM) is disclosed, including steps as follows. An electrothermal coupling model is constructed to obtain real-time junction temperature data. The original LSTM algorithm is improved to obtain a segmented LSTM prediction network for the aging characteristics of the IGBT. The monitoring value of the IGBT aging parameter is used to perform segmented LSTM prediction to obtain the predicted aging process, and the threshold values of different aging stages are categorized. An aging correction is performed on the aging parameter of the electrothermal coupling model to ensure the accuracy of the junction temperature data. Rainflow-counting algorithm is used to calculate real-time thermal stress load distribution of the IGBT. The fatigue damage theory and the Lesit life prediction model are combined to calculate the real-time cumulative damage and predicted life of the IGBT.

Abstract: Charging/recharging systems and charge status indicators are provided. In one implementation, a charge status indicator includes a charge sensing device configured to sense the charge of a rechargeable power supply. The charge status indicator further includes a detection device configured to compare the sensed charge with a plurality of predetermined levels in order to determine one of a plurality of capacity ranges of the rechargeable power supply. The charge status indicator also includes a first light emitting diode (LED), a second LED, and a switching circuit configured to switch the first and second LEDs on and off using a plurality of predefined illumination patterns to indicate the capacity range of the rechargeable power supply.

Abstract: A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in to which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory.

Abstract: A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory.

Abstract: A method and apparatus for congestion and fault management with time-to-live (TTL) have been disclosed. Each time a packet is transferred into an Egress Port's Final Buffer, an associated TTL Timeout Counter will be loaded with a value. If the packet cannot be transferred out of the Egress Port before TTL timeout, it will be purged by removing a memory buffer pointer from the corresponding Virtual Output Queue (VOQ) entry.

Abstract: A method and apparatus for congestion and fault management with time-to-live (TTL) have been disclosed. Each time a packet is transferred into an Egress Port's Final Buffer, an associated TTL Timeout Counter will be loaded with a value. If the packet cannot be transferred out of the Egress Port before TTL timeout, it will be purged by removing a memory buffer pointer from the corresponding Virtual Output Queue (VOQ) entry.

Abstract: A method and apparatus for unified final buffer with pointer-based and page-based scheme for traffic optimization have been disclosed.

Abstract: A serial buffer transports packets through queues capable of operating in a packet mode or a raw data mode. In packet mode, entire packets are stored in a queue. In raw data mode, packet header/delimiter information is not stored in the queue (only packet data is stored). Packets can be transferred out of a queue in response to a slave read request. The serial buffer constructs a packet header in response to the slave read request, and retrieves a specified amount of packet data from the selected queue. The serial buffer also transfers out packets as a bus master when a water level exceeds a water mark within a queue. The serial buffer constructs packet headers for these bus master transfers, which may be performed in a flush mode or a non-flush mode (in packet mode), or in a flush mode (in raw data mode).

Abstract: A method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer (RT) and continuous transfer (CT) modes have been disclosed where outstanding packets to be processed is through a Retransmission Mapper with a VOQ read pointer realignment that can quickly optimize network traffic with multiple VCs and mixed RT/CT modes.

Abstract: A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.

Abstract: A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory.

Abstract: In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame.

Abstract: A method and apparatus for dynamic traffic management with packet classification have been disclosed where packet size, variation, and count may be used to select credit or packet based arbitration.

Abstract: A method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switches have been disclosed where a buffer availability is based on a programmable reservation size for dynamic allocation.

Abstract: A serial buffer includes a first port configured to operate in accordance with a first serial protocol and a second port configured to operate in accordance with a second serial protocol. A first translation circuit of the serial buffer allows packets received on the first port to be translated to the second serial protocol, and then transferred to the second port. A second translation circuit of the serial buffer allows packets received on the second port to be translated to the first serial protocol, and then transferred to the first port. Translations may be performed in response to information included in the headers of the received packets, including source ID values, destination ID values and/or case number values.

Abstract: Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block, the memory block is removed from the used buffer pointer list and added to a request buffer pointer list. If a corresponding response packet is received within a timeout period, the memory block is transferred from the request buffer pointer list to the free buffer pointer list. Otherwise, the memory block is transferred from the request buffer pointer list to the used buffer pointer list.